參數(shù)資料
型號： AD9910BSVZ-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
中文描述： SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100
封裝： ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁數(shù)： 58/60頁
文件大小： 764K
代理商： AD9910BSVZ-REEL
AD9910
Multichip Sync Register
Address 0x0A, 4 bytes are assigned to this register.
Rev. 0 | Page 58 of 60
Table 25. Multichip Sync Register
Bit(s)
31:28
Descriptor
Sync Validation Delay
Explanation
This 4-bit number sets the timing skew (in ~150 ps increments) between SYSCLK and the
delayed sync-in signal for the sync validation block in the sync receiver. Default is 0000
2
.
0 = synchronization clock receiver disabled (default).
1 = synchronization clock receiver enabled.
0 = synchronization clock generator disabled (default).
1 = synchronization clock generator enabled.
0 = synchronization clock generator coincident with the rising edge of SYSCLK (default).
1 = synchronization clock generator coincident with the falling edge of SYSCLK.
This 6-bit number is the state that the internal clock generator assumes when it receives a
sync pulse. Default is 000000
2
.
This 5-bit number sets the output delay (in ~150 ps increments) of the sync generator.
Default is 00000
2
.
This 5-bit number sets the input delay (in ~150 ps increments) of the sync receiver. Default
is 00000
2
.
27
26
25
24
23:18
Sync Receiver Enable
Sync Generator Enable
Sync Generator Polarity
Not Available
Sync State Preset Value
17:16
15:11
Not Available
Output Sync Generator
Delay
Not Available
Input Sync Receiver Delay
10:8
7:3
2:0
Digital Ramp Limit Register
Address 0x0B, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Not Available
Table 26. Bit Descriptions for Digital Ramp Limit Register
Bit(s)
Descriptor
63:32
Digital Ramp Upper Limit
31:0
Digital Ramp Lower Limit
Digital Ramp Step Size Register
Address 0x0C, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 27. Bit Descriptions for Digital Ramp Step Size Register
Bit(s)
Descriptor
Explanation
63:32
Digital Ramp Decrement
Step Size
31:0
Digital Ramp Increment
Step Size
Digital Ramp Rate Register
Address 0x0D, 4 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 28. Bit Descriptions for Digital Ramp Rate Register
Bit(s)
Descriptor
Explanation
31:16
Digital Ramp Negative
Slope Rate
values.
15:0
Digital Ramp Positive Slope
Rate
values.
Explanation
32-bit digital ramp upper limit value.
32-bit digital ramp lower limit value.
32-bit digital ramp decrement step size value.
32-bit digital ramp increment step size value.
16-bit digital ramp negative slope value that defines the time interval between decrement
16-bit digital ramp positive slope value that defines the time interval between increment
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