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參數(shù)資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 55/60頁 |
| 文件大?。?/td> | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
Control Function Register 2 (CFR2)
Address 0x01; 4 bytes are assigned to this register.
Rev. 0 | Page 55 of 60
Table 18. Bit Descriptions for CFR2
Bit(s)
Descriptor
31:26
Not Available
25
DROVER Pin Active
24
23
Internal I/O Update Active
Explanation
Ineffective unless Bit 19 = 1. Refer to DROVER Pin section for details.
Ineffective if Bit 19 = 1 or CFR1<31> = 1 or CFR1<9> = 1.
0 = the amplitude scaler is bypassed and shut down for power conservation (default).
1 = the amplitude is scaled by the ASF from the active profile.
This bit is effective without the need for an I/O update.
0 = serial I/O programming is synchronized with the external assertion of the
I/O_UPDATE pin, which is configured as an input pin (default).
1 = serial I/O programming is synchronized with an internally generated I/O update
signal (the internally generated signal appears at the I/O_UPDATE pin, which is
configured as an output pin).
Enable Amplitude Scale
from Single Tone Profiles
22
SYNC_CLK Enable
0 = The SYNC_CLK pin is disabled; static Logic 0 output.
1 = the SYNC_CLK pin generates a clock signal at f
SYSCLK
; used for synchronization of the
serial I/O port (default).
See Table 11 for details. Default is 00
2
. See Digital Ramp Generator (DRG) section for details.
0 = disables digital ramp generator functionality (default).
1 = enables digital ramp generator functionality.
See Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell high functionality (default).
1 = enables no-dwell high functionality.
See Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell low functionality (default).
1 = enables no-dwell low functionality.
0 = a serial I/O port read operation of the FTW register reports the contents of the FTW
register (default).
1 = a serial I/O port read operation of the FTW register reports the actual 32-bit word
appearing at the input to the DDS phase accumulator.
Ineffective unless Bit 23 = 1. Sets the prescale ratio of the divider that clocks the auto I/O
update timer as follows:
00 = divide-by-1 (default).
01 = divide-by-2.
10 = divide-by-4.
11 = divide-by-8.
0 = the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal
continues to operate and provide timing to the data assembler.
1 = the internal PDCLK signal appears at the PDCLK pin (default).
0 = normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).
1 = inverted PDCLK polarity.
0 = no inversion.
1 = inversion.
0 = simultaneous application of amplitude, phase, and frequency changes to the DDS
arrive at the output in the order listed (default).
1 = simultaneous application of amplitude, phase, and frequency changes to the DDS
arrive at the output simultaneously.
21:20
19
18
17
16
Digital Ramp Destination
Digital Ramp Enable
Digital Ramp No-Dwell High
Digital Ramp No-Dwell Low
Read Effective FTW
15:14
I/O Update Rate Control
13:12
11
Not Available
PDCLK Enable
10
9
8
7
PDCLK Invert
TxEnable Invert
Not Available
Matched Latency Enable
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