參數(shù)資料
型號(hào): AD9910BSVZ-REEL
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
中文描述: SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100
封裝: ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁(yè)數(shù): 28/60頁(yè)
文件大?。?/td> 764K
代理商: AD9910BSVZ-REEL
AD9910
The direction of the ramping function is controlled by the
DRCTL pin. A Logic 0 on this pin causes the DRG to ramp
with a negative slope, whereas a Logic 1 causes the DRG to
ramp with a positive slope.
Rev. 0 | Page 28 of 60
The DRG also supports a hold feature controlled via the DRHOLD
pin. When this pin is Logic 1, the DRG is stalled at its last state,
otherwise, the DRG operates normally.
The DDS signal control parameters that are not the destination of
the DRG are taken from the active profile.
DDS CLOCK
D
Q
R
LOWER
LIMIT
0
1
DECREMENT STEP SIZE
PRESET
LOAD
Q
DRCTL
CLEAR DIGITAL RAMP ACCUMULATOR
AUTOCLEAR DIGITAL RAMP ACC
NO DWELL
LIMIT CONTROL
DIGITAL RAMP ACCUMULATOR
INCREMENT STEP SIZE
32
32
0
1
NEGATIVE SLOPE RATE
POSITIVE SLOPE RATE
16
16
32
16
62
DRHOLD
63
32
32
LOAD
CONTROL
LOGIC
LOAD LRR AT I/O_UPDATE
DIGITAL
RAMP
TIMER
ACCUMULATOR
RESET
CONTROL
LOGIC
NO-DWELL
CONTROL
2
32
32
TO DDS
SIGNAL
CONTROL
PARAMETER
UPPER
LIMIT
32
0
Figure 38. Digital Ramp Generator Detail
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