參數(shù)資料
型號(hào)： AD9910BSVZ-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
中文描述： SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100
封裝： ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁(yè)數(shù)： 39/60頁(yè)
文件大?。?/td> 764K
代理商： AD9910BSVZ-REEL
AD9910
Rev. 0 | Page 39 of 60
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
1
Δ
t
Δ
t
RAM ADRESS
RAM_SWP_OVER
I/O_UPDATE
M DDS CLOCK CYCLES
1
2
3
0
Figure 47. Continuous Bidirectional Ramp Timing Diagram
A change in state of the profile pins aborts the current waveform
and the newly selected RAM profile is used to initiate a new
waveform.
The RAM_SWP_OVR pin switches to Logic 1 when the state
machine reaches the waveform end address, then returns to
Logic 0 at the waveform start address, toggling each time one
of these addresses is reached.
A graphic representation of the continuous bidirectional ramp
mode is shown in Figure 47. The circled numbers indicate specific
events as follows:
Event 1—An I/O update or profile change has activated the RAM
continuous bidirectional ramp mode. The state machine initializes
to the waveform start address. The RAM_SWP_OVR pin resets to
Logic 0. The state machine begins incrementing through the
specified address range.
Event 2—The state machine reaches the waveform end address.
The RAM_SWP_OVR pin toggles to Logic 1.
Event 3—The state machine reaches the waveform start address.
The RAM_SWP_OVR pin toggles to Logic 0.
This action continues indefinitely until the next I/O update or
change in profile.
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