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參數(shù)資料
| 型號： | AD9910BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 36/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ-REEL |
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AD9910
Rev. 0 | Page 36 of 60
RAM_SWP_OVER
WAVEFORM START ADDRESS 0
WAVEFORM END ADDRESS 0
1
WAVEFORM START ADDRESS 1
WAVEFORM END ADDRESS 1
1
WAVEFORM END ADDRESS 2
1
RAM PROFILE
0
1
2
WAVEFORM START ADDRESS 2
RAM
ADDRESS
I/O_UPDATE
Δ
t
0
Δ
t
1
Δ
t
2
1
2
3
4
5
6
7
0
Figure 44. Internal Profile Control Timing Diagram (Burst)
The gray bar across the top indicates the time interval over
which the designated profile is in effect. The circled numbers
indicate specific events as follows:
Event 1—An I/O update registers the Internal Profile Control
bits (in Control Function Register 1) are as 0010. The
RAM_SWP_OVR pin is set to Logic 0. The state machine is
initialized to the waveform start address of RAM Profile 0 and
begins incrementing through the address range for RAM
Profile 0 at intervals of Δt
0
(as specified by the address step rate
for RAM Profile 0).
Event 2—The state machine reaches the waveform end address
of RAM Profile 0 and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 3—Having reached the waveform end address of RAM
Profile 0, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 1. The state machine
is initialized to the waveform start address of RAM Profile 1
and begins incrementing through the address range for RAM
Profile 1 at intervals of Δt
1
.
Event 4—The state machine reaches the waveform end address
of RAM Profile 1 and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 5—Having reached the waveform end address of RAM
Profile 1, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 2. The state machine
initializes to the waveform start address of RAM Profile 2 and
begins incrementing through the address range for RAM
Profile 2 at intervals of Δt
2
.
Event 6—The state machine reaches the waveform end address of
RAM Profile 2 and the RAM_SWP_OVR pin generates a positive
pulse spanning two DDS clock cycles.
Event 7—Having reached the waveform end address of RAM
Profile 2, the next expiration of the internal timer causes the
state machine to halt and marks completion of the burst
waveform generation process.
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