D7 I7 SCLK INSTRUCTIO" />
參數(shù)資料
型號(hào)： AD9854/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 33/52頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9854
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： AD9854 Eval Brd Schematic
AD9854 Eval Brd BOM
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
已用 IC / 零件： AD9854
已供物品： 板
相關(guān)產(chǎn)品： AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP
AD9854
Rev. E | Page 39 of 52
SDIO
D7
I7
SCLK
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I6
I5
I4
I3
I0
I2
I1
D6
D5
D4
D3
D2
D1
D0
CS
00
636
-0
58
Figure 58. Serial Port Write Timing Clock Stall Low
SDIO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SCLK
INSTRUCTION CYCLE
DON'T CARE
SDO
DATA TRANSFER CYCLE
I7
I6
I5
I4
I3
I0
I2
I1
CS
006
36-
059
Figure 59. 3-Wire Serial Port Read Timing Clock Stall Low
D7
D6
D5
D4
D3
D2
D1
D0
SDIO
SCLK
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I7
I6
I5
I4
I3
I0
I2
I1
CS
00
63
6-
06
0
Figure 60. Serial Port Write Timing Clock Stall High
I7
I6
I5
I4
I3
I0
I2
I1
SDIO
SCLK
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CS
006
36
-06
1
Figure 61. 2-Wire Serial Port Read Timing Clock Stall High
CR [8] is the internal update active bit. When this bit is set to
Logic 1, the I/O UD CLK pin is an output and the AD9854
generates the I/O UD CLK signal. When this bit is set to Logic 0,
external I/O UD CLK functionality is performed and the I/O
UD CLK pin is configured as an input.
CR [7] is reserved. Write to 0.
CR [6] is the inverse sinc filter bypass bit. When this bit is set,
the data from the DDS block goes directly to the output shaped
keying logic, and the clock to the inverse sinc filter is stopped.
Default is clear with the filter enabled.
CR [5] is the shaped keying enable bit. When this bit is set, the
output ramping function is enabled and is performed in
accordance with the CR [4] bit requirements.
CR [4] is the internal/external output shaped keying control bit.
When this bit is set to Logic 1, the output shaped keying factor is
internally generated and applied to both the I and Q paths.
When this bit is cleared (default), the output shaped keying
function is externally controlled by the user, and the ouput
shaped keying factor is the value of the I and Q output shaped
keying factor register. The two registers that are the output
shaped keying factors also default low such that the output is off
at power-up until the device is programmed by the user.
CR [3:2] are reserved. Write to 0.
CR [1] is the serial port MSB-/LSB-first bit. Default is low,
MSB first.
CR [0] is the serial port SDO active bit. Default is low, inactive.
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