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參數(shù)資料
| 型號(hào)： | AD9854/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9854 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | AD9854 Eval Brd Schematic AD9854 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計(jì)時(shí)，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9854 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP |
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AD9854
Rev. E | Page 32 of 52
PROGRAMMING THE AD9854
The AD9854 register layout table (Table 8) contains information
for programming the chip for the desired functionality. Although
many applications require very little programming to configure
the AD9854, some use all 12 accessible register banks. The
AD9854 supports an 8-bit parallel I/O operation or an SPI-
compatible serial I/O operation. All accessible registers can be
written and read back in either I/O operating mode.
S/P SELECT (Pin 70) is used to configure the I/O mode.
Systems that use the parallel I/O mode must connect the S/P
SELECT pin to VDD. Systems that operate in the serial I/O mode
must tie the S/P SELECT pin to GND.
Regardless of the mode, the I/O port data is written to a buffer
memory and only affects operation of the part after the contents
of the buffer memory are transferred to the register banks. This
transfer of information occurs synchronously to the system
clock in one of two ways:
Internally, at a rate programmable by the user.
Externally, by the user. I/O operations can occur in the
absence of REFCLK, but the data cannot be moved from
the buffer memory to the register bank without REFCLK.
(See the Internal and External Update Clock section for
more details.)
MASTER RESET
The MASTER RESET pin must be held at logic high active
for a minimum of 10 system clock cycles. This initializes the
communications bus and loads the default values listed in the
Table 8 section.
Table 7. REFCLK Multiplier Control Register Values
Reference Multiplier
Multiplier Value
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4
0
1
0
5
0
1
0
1
6
0
1
0
7
0
1
8
0
1
0
9
0
1
0
1
10
0
1
0
1
0
11
0
1
0
1
12
0
1
0
13
0
1
0
1
14
0
1
0
15
0
1
16
1
0
17
1
0
1
18
1
0
1
0
19
1
0
1
20
1
0
1
0
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