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參數(shù)資料
| 型號(hào)： | AD9725 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 600+ MSPS D/A Converter |
| 中文描述： | 14位，600 MSPS的D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 267K |
| 代理商： | AD9725 |
Preliminary Technical Data
AD9725
SERIAL PORT INTERFACE REGISTER MAPS
Table 5. Mode Control via SPI Port
Address
Bit 7
Bit 6
COMMS
00
SDIODIR
DATADIR
01
DATA
02
DATAFMT
DDR
03
04
05
06
07
08
09
0A
0B
0C
VERSION
0D
RESERVED
RESERVED
CALMEMCK
0E
RESERVED
RESERVED
MEMRDWR
0F
CALSTAT
CALEN
MEMADDR
10
MEMADDR[7]
MEMADDR[6]
MEMDATA
11
RESERVED
RESERVED
Rev. PrA | Page 9 of 16
Bit 5
SWRST
DCLKPOLI
RESERVED
CALMEM[1]
XFERSTAT
MEMADDR[5]
MEMDATA[5]
Bit 4
SLEEP
RESERVED
DCLKPOLO
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CALMEM[0]
XFEREN
MEMADDR[4]
MEMDATA[4]
Bit 3
PDN
DISDCLKO
VERSION[3]
RESERVED
SMEMWR
MEMADDR[3]
MEMDATA[3]
Bit 2
RESERVED
1
SYNCMAN
VERSION[2]
CALCKDIV[2]
SMEMRD
MEMADDR[2]
MEMDATA[2]
Bit 1
RESERVED
SYNCUPD
VERSION[1]
CALCKDIV[1]
FMEMRD
MEMADDR[1]
MEMDATA[1]
Bit 0
EXREF
SYNCALRM
VERSION[0]
CALCKDIV[0]
UNCAL
MEMADDR[0]
MEMDATA[0]
1
Reserved registers should be set to Logic 0 (low state) during a write operation, and masked (ignored) during a read operation.
Table 6. SPI Register Definitions
Register
COMMCTRL(00)
SDIODIR
Bit
7
Direction
1
Default
0
Description
0: SDIO pin configured for input only during data
transfer
1: SDIO pin configured for input or output during data
transfer
0: Serial data uses MSB first format
1: Serial data uses LSB first format
1: Default all serial register bits, except address 00h
1: DAC output current off
1: All analog and digital circuitry, except serial
interface, off
RESERVED
RESERVED
0: Internal bandgap reference
0: Twos complement input data format
1: Unsigned binary input data format
0: Single Data Rate mode
1: Double Data Rate mode
0: Data latched on DATACLKIN rising edge
1: Data latched on DATACLKIN falling edge
0: Data latched on DATACLKOUT rising edge
1: Data latched on DATACLKOUT falling edge
0: DATACLKOUT enabled
1: DATACLKOUT disabled
0: Automatic synchronization initiated following a
SYNCALRM
1: Manual synchronization needed following a
SYNCALRM
DATADIR
6
1
0
SWRST
SLEEP
PDN
5
4
3
1
1
1
0
0
0
RESERVED
RESERVED
EXREF
DATACTRL(02)
DATAFMT
2
1
0
7
0
0
1
1
0
0
0
0
DDR
6
1
0
DCLKPOLI
5
1
0
DCLKPOLO
4
1
0
DISDCLKO
3
1
0
SYNCMAN
2
1
0
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| AD9725BSV | 14-Bit, 600+ MSPS D/A Converter |
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