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參數(shù)資料
| 型號(hào)： | AD9725 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 600+ MSPS D/A Converter |
| 中文描述： | 14位，600 MSPS的D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 267K |
| 代理商： | AD9725 |
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Preliminary Technical Data
AD9725
DIGITAL SPECIFICATIONS
Table 3. T
MIN
to T
MAX
, AVDD1, AVDD2, DBVDD = 3.3 V, ADVDD, ACVDD, CLKVDD, DVDD = 2.5 V , I
OUTFS
= 20 mA, unless
otherwise noted. Specifications subject to change without notice.
Parameter
Conditions
Digital Inputs
VCM = 0.875 V to 1.575 V
Differential Logic ‘1’
(put into footnote, and delete
column)
Differential Logic ‘0’
Logic ‘1’ current
Logic ‘0’ current
Differential Input Resistance
Differential Input Capacitance
Data Setup Time (t
DS
)
Data Hold Time (t
DH
)
Data Clock Output Delay ( t
DCO
)
Serial Control Bus
Maximum SCLK Frequency (fSCLK)
Minimum Clock Pulse Width High (t
PWH
)
Minimum Clock Pulse Width Low (t
PWL
)
Maximum Clock Rise/Fall Time
Minimum Data/Chip Select Set Up Time (t
DS
)
Minimum Data Hold Time (t
DH
)
Maximum Data Valid Time (t
DV
)
RESET Pulse Width
Inputs (SDI, SDIO, SCLK, CSB)
Logic ‘1’ Voltage
Logic ‘0’ Voltage
Logic ‘1’ Current
Logic ‘0’ Current
Input Capacitance
SDIO Output
Logic ‘1’ Voltage
Logic ‘0’ Voltage
Logic ‘1’ Current
Logic ‘0’ Current
Rev. PrA | Page 5 of 16
Min
0.1
Typ
Max
0.6
Unit
V
–0.6
15
30
30
25
0
1.5
2.1
–10
–10
DRVDD–0.6
30
30
3.5
3.5
100
3
0.9
–0.3
2.4
3
0
5
–0.1
1
30
0.9
+10
+10
0.4
50
50
V
mA
mA
W
pF
ns
ns
ns
MHz
ns
ns
ms
ns
ns
ns
ns
V
V
μA
μA
pF
V
V
mA
mA
DIGITAL TIMING INFORMATION
0
CLK
DB[15:0]
DATACLK_IN
DATACLK_OUT
t
DCO
t
DH
t
DS
Figure 2. Single Datarate (SDR) Mode
0
t
DCO
t
DS
t
DH
t
DH
t
DS
CLK
DB[15:0]
DATACLK_IN
DATACLK_OUT
Figure 3. Double Datarate (DDR) Mode
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