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參數(shù)資料
| 型號： | AD9725 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 600+ MSPS D/A Converter |
| 中文描述： | 14位，600 MSPS的D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 267K |
| 代理商： | AD9725 |
AD9725
Preliminary Technical Data
ANALOG OUTPUT
The analog output of the AD9725 is based around a high dyna-
mic range CMOS DAC core. The output consists of a different-
tial current source capable of up to 20 mA full-scale. The output
devices are PMOS and are capable of sourcing current into an
output termination within a compliance voltage range of ±1 V.
Excellent distortion, noise, and ACLR perfor-mance is achie-
vable to Nyquist at sample rates of 600 MSPS+.
Rev. PrA | Page 14 of 16
SPI PORT CONTROL
The AD9725 serial port is a flexible, synchronous serial com-
munications port allowing easy interface to many industry
standard microcontrollers and microprocessors. The serial I/O
is compatible with most synchronous transfer formats, inclu-
ding both the Motorola SPI and Intel SSR protocols. The inter-
face allows read/write access to all registers that configure the
AD9725. Single or multiple byte transfers are supported as well
as MSB first or LSB first transfer formats. The AD9725 serial
interface port can be configured as a single pin I/O (SDIO) or
two unidirectional pins for in/out (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL PORT
INTERFACE
There are two phases to a communication cycle with the
AD9725. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9725, and coincident with the
first eight SCLK rising edges. The instruction byte provides the
AD9725 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines the number of bytes
in the data transfer, the starting register address for the first byte
of the data transfer, and whether the upcoming data transfer is
read or write. The first eight SCLK rising edges of each com-
munication cycle are used to write the instruction byte into the
AD9725.
A Logic 1 on the CS pin followed by a Logic 0 will reset the SPI
port timing to the initial state of the instruction cycle. This is
true regardless of the present state of the internal registers or
the other signal levels present at the inputs to the SPI port. If the
SPI port is in the midst of an instruction cycle or a data transfer
cycle, none of the present data will be written.
The remaining SCLK edges are for Phase 2 of the communi-
cation cycle. Phase 2 is the actual data transfer between the
AD9777 and the system controller. Phase 2 of the communi-
cation cycle is a transfer of 1, 2, 3, or 4 data bytes as determined
by the instruction byte. Normally, using one multibyte transfer
is the preferred method. However, single byte data transfers are
useful to reduce CPU overhead when register access requires
1 byte only. Registers change immediately upon writing to the
last bit of each transfer byte.
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 7
Table 7
N1
N0
Description
0
0
Transfer 1 byte
0
1
Transfer 2 byte
1
0
Transfer 3 byte
1
1
Transfer 4 byte
R/W
Bit 7 of the instruction byte determines whether a read or a
write data transfer will occur after the instruction byte write.
Logic high indicates a read operation. Logic 0 indicates a write
operation. N1, N0 -Bits 6 and 5 of the instruction byte
determine the number of bytes to be transferred during the data
transfer cycle. The bit decodes are shown in the following table:
Table 8
MSB
I7
I6
I5
I4
R/W
N1
N0
A4
I3
A3
I2
A2
I1
A1
LSB
I0
A0
A4, A3, A2, A1, A0
Bits 4, 3, 2, 1, 0 of the instruction byte determine which register
is accessed during the data transfer portion of the communi-
cations cycle. For multibyte transfers, this address is the starting
byte address. The remaining register addresses are generated by
the AD9725.
SERIAL PORT INTERFACE PIN DESCRIPTION
SCLK (Serial Clock)
The serial clock pin is used to synchronize data to and from the
AD9725, and to run the internal state machines. The SCLK
maximum frequency is 15 MHz. All data input to the AD9725 is
registered on the rising edge of SCLK. All data is driven out of
the AD9725 on the falling edge of SCLK.
CSB (Chip Select)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications line. The SDO and SDIO pins will go to a high
impedance state when this input is high. Chip select should stay
low during the entire communication cycle.
SDIO
Serial data I/O. Data is always written into the AD9725 on this
pin. This pin, however, can be used as a bidirectional data line.
The configuration of this pin is controlled by Bit 7 of register
address 00h. The default is Logic 0, which configures the SDIO
pin as unidirectional.
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