參數(shù)資料
型號(hào)： AD9641BCPZ-80
廠商： Analog Devices Inc
文件頁數(shù)： 27/36頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 80MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，雙極
Data Sheet
AD9641
Rev. B | Page 33 of 36
JESD204A Link Control Register 1 (Address 0x60)
Bit 7—Open
Bit 6—Serial Tail Bit Enable
If this bit is set, unused tail bits are padded with a pseudo random
number sequence from a 31-bit LFSR (see JESD204A 5.1.4).
Bit 5—Serial Test Sample Enable
If set, JESD204A test samples are enabled, and the transport
layer test sample sequence (as specified in JESD204A section
5.1.6.2) sent on all link lanes.
Bit 4—Serial Lane Synchronization Enable
If this bit is set, lane synchronization is enabled. Both sides
perform lane sync; frame alignment character insertion uses
either /K28.3/ or /K28.7/ control characters (see JESD204A
5.3.3.4).
Bits[3:2]—Serial Lane Alignment Sequence Mode
00: initial lane alignment sequence disabled.
01: initial lane alignment sequence enabled.
10: reserved.
11: initial lane alignment sequence always on test mode; JESD204A
data link layer test mode where repeated lane alignment sequence is
sent on all lanes.
Bit 1—Frame Alignment Character Insertion Disable
If Bit 1 is set, the frame alignment character insertion is
disabled per JESD204A section 5.3.3.4.
Bit 0—Serial Transmit Link Power-Down
If Bit 0 is set high, the serial transmit link is held in reset with its
clock gated off. The JESD204A transmitter should be powered
down when changing any of the link configuration bits.
JESD204A Link Control Register 2 (Address 0x61)
Bits[7:6]—Local DSYNC Mode
00: individual/separate mode. Each link is controlled by a
separate DSYNC pin that independently controls code group
synchronization.
01: global mode. Any DSYNC signal causes the link to begin
code group synchronization.
10: DSYNC active mode. The DSYNC signal is active; force
code group synchronization.
11: DSYNC pin disabled.
Bit 5—DSYNC Pin Input Inverted
If this bit is set, the DSYNC pin of the link is inverted (active
high).
Bit 4—CMOS DSYNC Input
0: LVDS differential pair DSYNC input (default).
1: CMOS single-ended DSYNC input.
Bit 3—Open
Bit 2—Bypass 8b/10b Encoding
If this bit is set, the 8b/10b encoding is bypassed and the most
significant bits are set to 0.
Bit 1—Invert Transmit Bits
Setting this bit inverts the 10 serial output bits. This effectively
inverts the output signals.
Bit 0—Mirror Serial Output Bits
Setting this bit reverses the order of the 10b outputs.
JESD204A Link Control Register 3 (Address 0x62)
Bit 7—Disable CHKSUM
Setting this bit high disables the CHKSUM configuration
parameter. (For testing purposes only.)
Bit 6—Open
Bits[5:4]—Link Test Generation Input Selection
00: 16-bit test generation data injected at sample input to the link.
01: 10-bit test generation data injected at output of 8b/10b
encoder (at input to PHY).
10: reserved.
11: reserved.
Bit 3—Open
Bits[2:0]—Link Test Generation Mode
000: normal operation (test mode disabled).
001: alternating checkerboard.
010: 1/0 word toggle.
011: PN sequence, long.
100: PN sequence, short.
101: continuous/repeat user test mode. The most significant bits
from the user pattern (1, 2, 3, 4) are placed on the output for one
clock cycle and then repeated. (Output User Pattern 1, 2, 3, 4,
1, 2, 3, 4, 1, 2, 3, 4….)
110: single user test mode. The most significant bits from the user
pattern (1, 2, 3, 4) are placed on the output for one clock cycle,
and then all zeros are output. (Output User Pattern 1, 2, 3, 4;
then output all zeros.)
111: ramp output.
JESD204A Link Control Register 4 (Address 0x63)
Bits[7:0]—Initial Lane Alignment Sequence Repeat Count
Bits[7:0] specify the number of times the initial lane alignment
sequence (ILAS) is repeated. If 0 is programmed, the ILAS does
not repeat. If 1 is programmed, the ILAS repeats one time, and
so on. See Register 0x60, Bits[3:2] to enable the ILAS and for
a test mode to continuously enable the initial lane alignment
sequence.
JESD204A Device Identification (DID) Number
(Address 0x64)
Bits[7:0]—Serial Device Identification (DID) Number
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