參數(shù)資料
型號： AD9641BCPZ-80
廠商： Analog Devices Inc
文件頁數(shù)： 17/36頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 80MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 托盤
輸入數(shù)目和類型： 1 個差分，雙極
AD9641
Data Sheet
Rev. B | Page 24 of 36
Figure 67 shows an example of the digital output (default) data
eye and a time interval error (TIE) jitter histogram.
Additional SPI options allow the user to further increase the output
driver voltage swing of all four outputs to drive longer trace lengths
(see Address 0x15 in Table 17). Even though this produces sharper
rise and fall times on the data edges and is less prone to bit errors,
the power dissipation of the DRVDD supply increases when this
option is used. See the Memory Map section for more details.
The format of the output data is twos complement, by default.
Table 12 provides an example of this output coding format.
To change the output data format to offset binary or Gray code,
see the Memory Map section (Address 0x14 in Table 17).
The lowest typical clock rate is 40 MSPS. For clock rates slower
than 60 MSPS, Bit 3 should be set to 0 in the PLL control register
(Address 0x21 in Table 17). This option sets the PLL loop band-
width to use clock rates between 40 MSPS and 60 MSPS.
Setting Bit 2 in the output mode register (Address 0x14) allows
the user to invert the digital samples from their nominal state.
As shown in Figure 63, the MSB is transmitted first in the data
output serial stream.
–600
–200
–400
0
200
400
600
610
620
0
635
–0.5
0.5
TIME (ps)
ULS
400
200
0
–200
–400
V
O
LTA
GE
(
m
V)
HEIGHT1: EYE DIAGRAM
PERIOD1: HISTOGRAM
WIDTH@BER1: BATHTUB
1
–
20,000
25,000
15,000
10,000
5000
0
HI
T
S
615
625
630
100
10–2
10–4
10–6
10–8
10–10
10–12
10–14
BER
3
+
4
+
EYE: TRANSITION BITS
OFFSET: –0.004
UIS: 8000; 639999, TOTAL: 8000; 639999
0.781
09
210
-050
Figure 67. AD9641-80 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations
–300
–100
–200
0
100
200
300
305
315
0
330
335
–0.5
0.5
TIME (ps)
ULS
400
600
200
0
–200
–400
–600
VO
L
T
A
G
E
(
m
V)
HEIGHT1: EYE DIAGRAM
PERIOD1: HISTOGRAM
WIDTH@BER1: BATHTUB
1
–
300k
250k
350k
400k
200k
100k
150k
50k
0
HI
T
S
310
320 325
100
10–2
10–4
10–6
10–8
10–10
10–12
10–14
BE
R
3
–
4
–
0.75
09
210
-06
8
EYE: TRANSITION BITS
OFFSET: –0.002
UIS: 8000; 1239996, TOTAL: 48000; 7439996
Figure 68. AD9641-155 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations
Table 12. Digital Output Coding
Code
(VIN+) (VIN), Input Span = 1.75 V p-p (V)
Digital Output Twos Complement ([D13:D0])
8191
+0.875
01 1111 1111 1111
0
0.00
00 0000 0000 0000
1
0.000107
11 1111 1111 1111
8192
0.875
10 0000 0000 0000
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AD9641BCPZRL7-80 功能描述:14 Bit Analog to Digital Converter 1 Input 1 Pipelined 32-LFCSP-WQ (5x5) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 位數(shù):14 采樣率（每秒）:80M 輸入數(shù):1 輸入類型:差分 數(shù)據(jù)接口:JESD204A 配置:S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):管線 參考類型:內(nèi)部 電壓 - 電源，模擬:1.7 V ~ 1.9 V 電壓 - 電源，數(shù)字:1.7 V ~ 1.9 V 特性:- 工作溫度:-40°C ~ 85°C 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1,500
AD9642 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
AD9642-170EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14 Bit 170 Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
AD9642-210EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14 Bit 210 Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
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