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| 型號(hào)： | AD9641BCPZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SRL 80MSPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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AD9641
Data Sheet
Rev. B | Page 20 of 36
Input Clock Divider
The AD9641 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
For divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS)
is optional. For other divide ratios, such as 3, 5, 6, 7, and 8, the
DCS must be enabled for proper part operation.
The AD9641 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x03A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. The AD9641 requires a tight
tolerance on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9641 contains a DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD9641. Noise and distortion performance are nearly flat for a
wide range of duty cycles with the DCS enabled.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
of less than 20 MHz, nominally. The loop has a time constant
associated with it that must be considered in applications in
which the clock rate can change dynamically. A wait time of
1.5 μs to 5 μs is required after a dynamic clock frequency
increase or decrease before the DCS loop is relocked to the
input signal. During the time when the loop is not locked, the
DCS loop is bypassed, and internal device timing is dependent
on the duty cycle of the input clock signal. In such applications,
it may be appropriate to disable the DCS. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. For inputs near full scale, the degradation in
SNR from the low frequency SNR (SNRLF) at a given input
frequency (fINPUT) due to jitter (tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
)
10
/
(
LF
SNR
]
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 59. The measured curve
in Figure 59 was taken using an ADC clock source with approxi-
mately 65 fS of jitter, which combines with the 125 fS of jitter
inherent in the AD9641 to produce the result shown.
50
55
60
65
70
75
1
10
100
1000
S
NR
(
d
BF
S
)
INPUT FREQUENCY (MHz)
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
09
21
0-
0
4
1
Figure 59. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9641.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756 Application
Note for more information about jitter performance as it relates
to ADCs.
CHIP SYNCHRONIZATION
The AD9641 has a SYNC input that offers the user flexible
synchronization options for synchronizing the clock divider.
The clock divider sync feature is useful for guaranteeing synchro-
nized sample clocks across multiple ADCs. The input clock
divider can be enabled to synchronize on a single occurrence of
the SYNC signal or on every occurrence.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally syn-
chronized to the input clock signal, meeting the setup and hold
times shown in Table 5. The SYNC input should be driven using
a single-ended CMOS-type signal.
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| AD9641BCPZRL7-155 | 制造商:Analog Devices 功能描述:14BIT 155MSPS ADC W/JESD204A - Tape and Reel 制造商:Analog Devices 功能描述:IC ADC 14BIT SRL 155MSPS 32LFCSP |
| AD9641BCPZRL7-80 | 功能描述:14 Bit Analog to Digital Converter 1 Input 1 Pipelined 32-LFCSP-WQ (5x5) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 位數(shù):14 采樣率（每秒）:80M 輸入數(shù):1 輸入類型:差分 數(shù)據(jù)接口:JESD204A 配置:S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):管線 參考類型:內(nèi)部 電壓 - 電源，模擬:1.7 V ~ 1.9 V 電壓 - 電源，數(shù)字:1.7 V ~ 1.9 V 特性:- 工作溫度:-40°C ~ 85°C 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1,500 |
| AD9642 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC) |
| AD9642-170EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14 Bit 170 Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9642-210EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14 Bit 210 Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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