參數(shù)資料
型號(hào)： AD9641BCPZ-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/36頁(yè)
文件大小： 0K
描述： IC ADC 14BIT SRL 80MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，雙極
AD9641
Data Sheet
Rev. B | Page 26 of 36
There are nine digital output test pattern options available that
can be initiated through the SPI (see Table 14 for the output bit
sequencing options). This feature is useful when validating
receiver capture and timing. Some test patterns have two serial
sequential words and can be alternated in various ways, depending
on the test pattern selected. Note that some patterns do not
adhere to the data format select option. In addition, custom
user-defined test patterns can be assigned in the user pattern
registers (Address 0x19 and Address 0x20).
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 1 (511) bits. A description
of the PN sequence short and how it is generated can be found
in Section 5.1 of the ITU-T O.150 (05/96) recommendation.
The only difference is that the starting value must be a specific
value instead of all 1s (see Table 13 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 1 (8,388,607) bits.
A description of the PN sequence long and how it is generated
can be found in Section 5.6 of the ITU-T O.150 (05/96) standard.
The only differences are that the starting value must be a specific
value instead of all 1s (see Table 13 for the initial values) and
that the AD9641 inverts the bit stream with relation to the ITU-T
standard.
Table 13. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First)
PN Sequence Short
0x0092
0x125B, 0x3C9A, 0x2660
PN Sequence Long
0x3AFF
0x3FD7, 0x0002, 0x36E0
Register 0x62 allows patterns that are similar to those described
in Table 14 to be input at different points along the datapath.
This allows the user to provide predictable output data on the
serial link without it having been manipulated by the internal
formatting logic. Refer to Table 17 for additional information
on the test modes available in Register 0x62.
Table 14. Flexible Output Test Modes from SPI Register 0x0D
Output Test Mode
Bit Sequence
Pattern Name
Digital Output Word 1 (Default
Twos Complement Format)
Digital Output Word 2 (Default
Twos Complement Format)
Subject to Data
Format Select
0000
Off (default)
Not applicable
Yes
0001
Midscale short
00 0000 0000 0000
Same
Yes
0010
+Full-scale short
01 1111 1111 1111
Same
Yes
0011
Full-scale short
10 0000 0000 0000
Same
Yes
0100
Checkerboard
10 1010 1010 1010
01 0101 0101 0101
No
0101
PN sequence long
Not applicable
Yes
0110
PN sequence short
Not applicable
Yes
0111
One-/zero-word toggle
1111 1111 1111
0000 0000 0000
No
1000
User test mode
User data from Register 0x19 to
Register 0x20
User data from Register 0x19 to
Register 0x20
Yes
1001 to 1110
Not used
Not applicable
1111
Ramp output
N
N + 1
No
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