參數(shù)資料
型號： AD9641BCPZ-80
廠商： Analog Devices Inc
文件頁數(shù)： 15/36頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 80MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，雙極
AD9641
Data Sheet
Rev. B | Page 22 of 36
Figure 61 shows a simplified block diagram of the JESD204A link
for the AD9641. The 8b/10b encoding works by taking eight bits of
data (an octet) and encoding them into a 10-bit symbol. By default
in the AD9641, the 14-bit converter word is broken into two octets.
Bit 13 through Bit 6 are in the first octet. The second octet contains
Bit 5 through Bit 0 and two tail bits. The MSB of the tail bits can
also be used to indicate an out-of-range condition. The tail bits
are configured using the JESD204A link control in JESD204A
Link Control Register 1, Address 0x60, Bit 6.
AD9641 ADC
JESD204 A LINK
(M = 0, 1; L = 0, 1)
CONVERTER
SAMPLE
OUTPUT
LANE
CONVERTER
INPUT
LINK
DSYNC
CONVERTER
09210
-043
Figure 61. AD9641 Transmit Link Simplified Block Diagram
The two resulting octets are optionally scrambled and encoded
into their corresponding 10-bit code. The scrambler function is
controlled by the JESD204A scrambling and lane configuration
register, Address 0x06E, Bit 7. Figure 62 shows how the 14-bit
data is taken from the ADC, the tail bits are added, the two octets
are scrambled, and the octets are encoded into two 10-bit symbols.
Figure 63 illustrates the default data format.
The scrambler uses a self-synchronizing, polynomial-based
algorithm defined by the following equation: 1 + x14 + x15. The
descrambler in the receiver should be a self-synchronizing
version of the scrambler polynomial. Figure 64 shows the
corresponding receiver data path.
Refer to JEDEC Standard No. 204A, April 2008, Section 5.1, for
complete transport layer and data format details. See Section 5.2
for a complete explanation of scrambling and descrambling.
DATA
FROM
ADC
FRAME
ASSEMBLER
(ADD TAIL BITS)
OPTIONAL
SCRAMBLER
1 + x14 + x15
8B/10B
ENCODER
TO
RECEIVER
09
21
0-
04
4
Figure 62. ADC Output Data Path
WORD 0[13:6]
SYMBOL 0[9:0]
WORD 0[5:0], TAIL BITS[1:0]
SYMBOL 1[9:0]
WORD 1[13:6]
SYMBOL 2[9:0]
WORD 1[5:0], TAIL BITS[1:0]
SYMBOL 3[9:0]
TIME
FRAME 0
FRAME 1
09
21
0-
0
45
Figure 63. 14-Bit Data Transmission with Tail Bits
8B/10B
DECODER
OPTIONAL
DESCRAMBLER
1 + x14 + x15
FRAME
ALIGNMENT
DATA
OUT
FROM
TRANSMITTER
09
21
0
-04
6
Figure 64. Required Receiver Data Path
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AD9642 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
AD9642-170EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14 Bit 170 Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
AD9642-210EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14 Bit 210 Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
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