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參數(shù)資料
| 型號： | AD9627ABCPZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 80MSPS 64LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 490mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9627
Rev. B | Page 15 of 76
ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter
Rating
ELECTRICAL
AVDD, DVDD to AGND
0.3 V to +2.0 V
DRVDD to DRGND
0.3 V to +3.9 V
AGND to DRGND
0.3 V to +0.3 V
AVDD to DRVDD
3.9 V to +2.0 V
VIN+A/VIN+B, VINA/VINB to AGND
0.3 V to AVDD + 0.2 V
CLK+, CLK to AGND
0.3 V to +3.9 V
SYNC to AGND
0.3 V to +3.9 V
VREF to AGND
0.3 V to AVDD + 0.2 V
SENSE to AGND
0.3 V to AVDD + 0.2 V
CML to AGND
0.3 V to AVDD + 0.2 V
RBIAS to AGND
0.3 V to AVDD + 0.2 V
CSB to AGND
0.3 V to +3.9 V
SCLK/DFS to DRGND
0.3 V to +3.9 V
SDIO/DCS to DRGND
0.3 V to DRVDD + 0.3 V
SMI SDO/OEB
0.3 V to DRVDD + 0.3 V
SMI SCLK/PDWN
0.3 V to DRVDD + 0.3 V
SMI SDFS
0.3 V to DRVDD + 0.3 V
D0A/D0B through D11A/D11B to
DRGND
0.3 V to DRVDD + 0.3 V
FD0A/FD0B through FD3A/FD3B to
DRGND
0.3 V to DRVDD + 0.3 V
DCOA/DCOB to DRGND
0.3 V to DRVDD + 0.3 V
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
40°C to +85°C
Maximum Junction Temperature
Under Bias
150°C
Storage Temperature Range
(Ambient)
65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
Table 10. Thermal Resistance
Package
Type
Airflow
Velocity
(m/s)
θJA1,2
θJC1,3
Unit
64-Lead LFCSP
9 mm × 9 mm
(CP-64-6)
0
18.8
0.6
6.0
°C/W
1.0
16.5
°C/W
2.0
15.8
°C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown, airflow improves heat dissipation, which
reduces θJA. In addition, metal in direct contact with the package
leads from metal traces, through holes, ground, and power
planes, reduces the θJA.
ESD CAUTION
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