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參數(shù)資料
型號: AD9627ABCPZ-80
廠商: Analog Devices Inc
文件頁數(shù): 5/76頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 80MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 490mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
輸入數(shù)目和類型: 4 個單端,單極;2 個差分,單極
AD9627
Rev. B | Page 13 of 76
TIMING SPECIFICATIONS
Table 8.
Parameter
Conditions
Min
Typ
Max
Unit
SYNC TIMING REQUIREMENTS
tSSYNC
SYNC to rising edge of CLK setup time
0.24
ns
tHSYNC
SYNC to rising edge of CLK hold time
0.40
ns
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
SCLK pulse width high
10
ns
tLOW
SCLK pulse width low
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
10
ns
SPORT TIMING REQUIREMENTS
tCSSCLK
Delay from rising edge of CLK+ to rising edge of SMI SCLK
3.2
4.5
6.2
ns
tSSCLKSDO
Delay from rising edge of SMI SCLK to SMI SDO
0.4
0
0.4
ns
tSSCLKSDFS
Delay from rising edge of SMI SCLK to SMI SDFS
0.4
0
0.4
ns
Timing Diagrams
CLK+
DCOA/DCOB
CH A/CH B DATA
N
N+ 1
N+ 2
N+ 3
N+ 4
N+ 5
N+ 6
N+ 7
N+ 8
N – 12
N – 11
N – 9
N – 8
N – 7
N – 6
N – 5
N – 4
N – 13
CLK–
tCLK
tPD
tS
tH
tDCO
tCLK
tA
CH A/CH B FAST
DETECT
N – 1
N + 2
N + 3
N + 4
N + 5
N + 6
N – 3
N – 2
N – 10
N + 1
N
06
57
1-
0
02
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
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