參數(shù)資料
型號(hào)： AD9627ABCPZ-80
廠商： Analog Devices Inc
文件頁數(shù)： 41/76頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 80MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 490mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 4 個(gè)單端，單極；2 個(gè)差分，單極
AD9627
Rev. B | Page 46 of 76
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x109
Fine Lower
Threshold
Register 1
(Local)
Open
Fine Lower Threshold[12:8]
0x00
0x10A
Increase Gain
Dwell Time
Register 0
(Local)
Increase Gain Dwell Time[7:0]
0x00
In ADC clock
cycles
0x10B
Increase Gain
Dwell Time
Register 1
(Local)
Increase Gain Dwell Time[15:8]
0x00
In ADC clock
cycles
0x10C
Signal Monitor
DC Correction
Control
(Global)
Open
DC
correction
freeze
DC Correction Bandwidth[3:0]
DC
correction
for signal
path
enable
DC
correction
for signal
monitor
enable
0x00
0x10D
Signal Monitor
DC Value
Channel A
Register 0
(Global)
DC Value Channel A[7:0]
Read only
0x10E
Signal Monitor
DC Value
Channel A
Register 1
(Global)
Open
DC Value Channel A[13:8]
Read only
0x10F
Signal Monitor
DC Value
Channel B
Register 0
(Global)
DC Value Channel B[7:0]
Read only
0x110
Signal Monitor
DC Value
Channel B
Register 1
(Global)
Open
DC Value Channel B[13:8]
Read only
0x111
Signal Monitor
SPORT Control
(Global)
Open
RMS/MS
magnitude
output
enable
Peak
detector
output
enable
Threshold
crossing
output
enable
SPORT SMI
SCLK divide
00 = undefined
01 = divide by 2
10 = divide by 4
11 = divide by 8
SPORT
SMI SCLK
sleep
Signal
monitor
SPORT
output
enable
0x04
0x112
Signal Monitor
Control
(Global)
Complex
power
calculation
mode
enable
Open
Signal
monitor
rms/ms
select
0 = rms
1 = ms
Signal monitor mode
00 = rms/ms magnitude
01 = peak detector
10 = threshold crossing
11 = threshold crossing
Signal
monitor
enable
0x00
0x113
Signal Monitor
Period
Register 0
(Global)
Signal Monitor Period[7:0]
0x80
In ADC clock
cycles
0x114
Signal Monitor
Period
Register 1
(Global)
Signal Monitor Period[15:8]
0x00
In ADC clock
cycles
0x115
Signal Monitor
Period
Register 2
(Global)
Signal Monitor Period[23:16]
0x00
In ADC clock
cycles
0x116
Signal Monitor
Result
Channel A
Register 0
(Global)
Signal Monitor Result Channel A[7:0]
Read only
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