參數資料
型號: AD9627ABCPZ-80
廠商: Analog Devices Inc
文件頁數: 35/76頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 80MSPS 64LFCSP
標準包裝: 1
位數: 12
采樣率(每秒): 80M
數據接口: 串行,SPI?
轉換器數目: 2
功率耗散(最大): 490mW
電壓電源: 模擬和數字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
輸入數目和類型: 4 個單端,單極;2 個差分,單極
AD9627
Rev. B | Page 40 of 76
CHANNEL/CHIP SYNCHRONIZATION
The AD9627 has a SYNC input that offers the user flexible
synchronization options for synchronizing the internal blocks.
The clock divider sync feature is useful for guaranteeing synchro-
nized sample clocks across multiple ADCs. The signal monitor
block can also be synchronized using the SYNC input, allowing
properties of the input signal to be measured during a specific
time period. The input clock divider can be enabled to synchronize
on a single occurrence of the SYNC signal or on every occurrence.
The signal monitor block is synchronized on every SYNC input
signal.
The SYNC input is internally synchronized to the sample clock;
however, to ensure there is no timing uncertainty between multiple
parts, the SYNC input signal should be externally synchronized to
the input clock signal, meeting the setup and hold times shown
in Table 8. The SYNC input should be driven using a single-
ended CMOS-type signal.
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