參數(shù)資料
型號： AD9522-4/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 33/84頁
文件大小： 0K
描述： BOARD EVAL FOR AD9522-4 CLK GEN
設(shè)計資源： AD9522 Eval Board Schematic
AD9522 BOM
標準包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9522-4
主要屬性： 12 LVDS/24 CMOS 輸出，1.6 GHz VCO
次要屬性： I²C & SPI 接口
已供物品： 板
AD9522-4
Rev. 0 | Page 39 of 84
NO
YES
PLL ENABLED
DLD == LOW
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
HIGH IMPEDANCE
CHARGE PUMP
REFERENCE
EDGE AT PFD?
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
DLD == HIGH
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
(0x01D[3] = 1; USE LD PIN VOLTAGE
WITH HOLDOVER.
0x01D[3] = 0; IGNORE LD PIN VOLTAGE,
TREAT LD PIN AS ALWAYS HIGH.)
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
RETURNS.
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF THE DLD
DELAY COUNTER) WITH THE REFERENCE AND
FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT
THE PFD. THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK
BEFORE THE HOLDOVER FUNCTION CAN BE
RETRIGGERED.
0
72
25
-06
9
Figure 47. Flowchart of Automatic/Internal Holdover Mode
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD (CSDLD) mode. It is possible
to disable the LD comparator (0x01D[3]), which causes the hold-
over function to always sense LD as high. If DLD is used, it is
possible for the DLD signal to chatter while the PLL is reacquiring
lock. The holdover function may retrigger, thereby preventing
the holdover mode from terminating. Use of the current source
lock detect mode is recommended to avoid this situation (see the
When in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
is reset synchronously with the charge pump leaving the high
impedance state on the reference path PFD event. This helps
align the edges out of the R and N dividers for faster settling of
the PLL and reduces frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and
R numbers are close because this results in a smaller phase
difference for the loop to settle out.
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