參數(shù)資料
型號: AD9522-4/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 22/84頁
文件大小: 0K
描述: BOARD EVAL FOR AD9522-4 CLK GEN
設(shè)計資源: AD9522 Eval Board Schematic
AD9522 BOM
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9522-4
主要屬性: 12 LVDS/24 CMOS 輸出,1.6 GHz VCO
次要屬性: I²C & SPI 接口
已供物品:
AD9522-4
Rev. 0 | Page 29 of 84
Mode 1: Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is <1600 MHz, a configuration that bypasses the
VCO divider can be used. This is the only difference from Mode 2.
Bypassing the VCO divider limits the frequency of the clock
source to <1600 MHz (due to the maximum input frequency
allowed at the channel dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
<1600 MHz, the register settings shown in Table 23 should be used.
Table 23. Settings for Clock Distribution < 1600 MHz
Register
Description
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off )
0x1E1[0] = 1b
Bypass the VCO divider as the source for
the distribution section
0x1E1[1] = 0b
CLK selected as the source
When using the internal PLL with an external VCO < 1600 MHz,
the PLL must be turned on.
Table 24. Settings for Using Internal PLL with External VCO
< 1600 MHz
Register
Description
0x1E1[0] = 1b
Bypass the VCO divider as the source for
the distribution section
0x010[1:0] = 00b
PLL normal operation (PLL on) along
with other appropriate PLL settings in
0x010 to 0x01E
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the VCO/
VCXO. This loop filter determines the loop bandwidth and stability
of the PLL. Make sure to select the proper PFD polarity for the
VCO/VCXO being used.
Table 25. Setting the PFD Polarity
Register
Description
0x010[7] = 0b
PFD polarity positive (higher control voltage
produces higher frequency)
0x010[7] = 1b
PFD polarity negative (higher control voltage
produces lower frequency)
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