參數(shù)資料
型號: AD9516-5BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 75/76頁
文件大?。?/td> 0K
描述: IC CLOCK GEN W/PLL 64-LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:14
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
AD9516-5
Rev. A | Page 8 of 76
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLK = 1 GHz, Output = 50 MHz
Input slew rate > 1 V/ns
Divider = 20
At 10 Hz Offset
124
dBc/Hz
At 100 Hz Offset
134
dBc/Hz
At 1 kHz Offset
142
dBc/Hz
At 10 kHz Offset
151
dBc/Hz
At 100 kHz Offset
157
dBc/Hz
At 1 MHz Offset
160
dBc/Hz
>10 MHz Offset
163
dBc/Hz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ABSOLUTE TIME JITTER
Application example based on a typical setup using
an external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R = 1
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
54
fs rms
Integration bandwidth = 200 kHz to 5 MHz
77
fs rms
Integration bandwidth = 200 kHz to 10 MHz
109
fs rms
Integration bandwidth = 12 kHz to 20 MHz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
79
fs rms
Integration bandwidth = 200 kHz to 5 MHz
114
fs rms
Integration bandwidth = 200 kHz to 10 MHz
163
fs rms
Integration bandwidth = 12 kHz to 20 MHz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
124
fs rms
Integration bandwidth = 200 kHz to 5 MHz
176
fs rms
Integration bandwidth = 200 kHz to 10 MHz
259
fs rms
Integration bandwidth = 12 kHz to 20 MHz
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL;
uses rising edge of clock signal
CLK = 622.08 MHz; LVPECL = 622.08 MHz;
Divider = 1
40
fs rms
Bandwidth = 12 kHz to 20 MHz
CLK = 622.08 MHz; LVPECL = 155.52 MHz;
Divider = 4
80
fs rms
Bandwidth = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVPECL = 100 MHz;
Divider = 16
215
fs rms
Calculated from SNR of ADC method; DCC not used
for even divides
CLK = 500 MHz; LVPECL = 100 MHz;
Divider = 5
245
fs rms
Calculated from SNR of ADC method; DCC on
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL;
uses rising edge of clock signal
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2
(VCO Divider Not Used)
85
fs rms
Bandwidth = 12 kHz to 20 MHz
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
113
fs rms
Bandwidth = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16
280
fs rms
Calculated from SNR of ADC method; DCC not used
for even divides
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL; uses
rising edge of clock signal
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
365
fs rms
Calculated from SNR of ADC method; DCC not used
for even divides
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