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參數(shù)資料
| 型號(hào)： | AD9516-5BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/76頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN W/PLL 64-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9516-5
Rev. A | Page 37 of 76
Table 32. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
DX
Output Duty Cycle
Input Clock
Duty Cycle
N + M + 2
DCCOFF = 1
DCCOFF = 0
Any
Channel
divider
bypassed
1 (divider
bypassed)
Same as input
duty cycle
Any
Even
(N + 1)/
(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/
(M + N + 2)
50%, requires
M = N + 1
X%
Odd
(N + 1)/
(M + N + 2)
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Phase Offset or Coarse Time Delay (0, 1, and 2)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 33).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset, or delay, the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register, plus the start high
(SH) bit for each channel divider. When the start high bit is set,
the delay is also affected by the number of low cycles (M) that
are programmed for the divider.
The sync function must be used to make phase offsets effective
(see the Synchronizing the Outputs—SYNC Function section).
Table 33. Setting Phase Offset and Division for Divider 0,
Divider 1, and Divider 21
Divider
Start
High (SH)
Phase
Offset (PO)
Low
Cycles (M)
High
Cycles (N)
0
0x191[4]
0x191[3:0]
0x190[7:4]
0x190[3:0]
1
0x194[4]
0x194[3:0]
0x193[7:4]
0x193[3:0]
2
0x197[4]
0x197[3:0]
0x196[7:4]
0x196[3:0]
1 Note that the value stored in the register = # of cycles minus 1. For example,
Register 0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0.
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX (in
seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15:
Δt = Φ × TX
Δc = Δt/TX = Φ
Case 2
For Φ ≥ 16:
Δt = (Φ 16 + M + 1) × TX
Δc = Δt/TX
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 43 shows the results of setting such a coarse
offset between outputs.
CHANNEL DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
01
234
567
89 10 11 12 13 14 15
Tx
DIVIDER 0
DIVIDER 1
DIVIDER 2
CHANNEL
DIVIDER INPUT
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
1 × Tx
2 × Tx
07
972-
071
Figure 43. Effect of Coarse Phase Offset (or Delay)
Channel Dividers—LVDS/CMOS Outputs
Channel Divider 3 and Channel Divider 4 each drive a pair of
LVDS outputs, giving four LVDS outputs (OUT6 to OUT9).
Alternatively, each of these LVDS differential outputs can be
configured individually as a pair (A and B) of CMOS single-
ended outputs, providing for up to eight CMOS outputs. By default,
the B output of each pair is off but can be turned on as desired.
Channel Divider 3 and Channel Divider 4 each consist of two
cascaded, 2 to 32, frequency dividers. The channel frequency
division is DX.1 × DX.2, or up to 1024. Divide-by-1 is achieved by
bypassing one or both of these dividers. Both of the dividers also
have DCC enabled by default, but this function can be disabled,
if desired, by setting the DCCOFF bit of the channel. A coarse
phase offset or delay is also programmable (see the Phase Offset
or Coarse Time Delay (Divider 3 and Divider 4) section). The
channel dividers operate up to 1600 MHz. The features and
settings of the dividers are selected by programming the
through Table 57).
Divider
M
N
Bypass
DCCOFF
3
3.1
0x199[7:4]
0x199[3:0]
0x19C[4]
0x19D[0]
3.2
0x19B[7:4]
0x19B[3:0]
0x19C[5]
0x19D[0]
4
4.1
0x19E[7:4]
0x19E[3:0]
0x1A1[4]
0x1A2[0]
4.2
0x1A0[7:4]
0x1A0[3:0]
0x1A1[5]
0x1A2[0]
1 Note that the value stored in the register = # of cycles minus 1. For example,
Register 0x199[7:4] = 0001b equals two low cycles (M = 2) for Divider 3.1.
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