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參數(shù)資料
| 型號： | AD9516-5BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN W/PLL 64-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9516-5
Rev. A | Page 29 of 76
PLL External Loop Filter
An example of an external loop filter for a PLL is shown in
Figure 36. A loop filter must be calculated for each desired PLL
configuration. The values of the components depend on the VCO
frequency, the KVCO, the PFD frequency, the charge pump current,
the desired loop bandwidth, and the desired phase margin. The
loop filter affects the phase noise, loop settling time, and loop
stability. A basic knowledge of PLL theory is helpful for under-
standing loop filter design. ADIsimCLK can help with calculation
of a loop filter according to the application requirements.
CLK/CLK
EXTERNAL
VCO/VCXO
CHARGE
PUMP
CP
C1
C2
C3
R1
R2
AD9516-5
07972-
065
Figure 36. Example of External Loop Filter for PLL
PLL Reference Inputs
The AD9516 features a flexible PLL reference input circuit that
allows a fully differential input or two separate single-ended
inputs. The input frequency range for the reference inputs is
specified in Table 2. Both the differential and the single-ended
inputs are self-biased, allowing for easy ac coupling of input signals.
The differential input and the single-ended inputs share two
pins, REFIN (REF1) and REFIN (REF2). The desired reference
input type is selected and controlled by Register 0x01C (see
and
).
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly (see Table 2) to prevent
chattering of the input buffer when the reference is slow or missing.
The specification for this voltage level is found in Table 2. The input
hysteresis increases the voltage swing required of the driver to
overcome the offset. The differential reference input can be driven
by either ac-coupled LVDS or ac-coupled LVPECL signals.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
Each single-ended input can be independently powered down
when not needed to increase isolation and reduce power. Either
a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential reference input is powered down whenever the
PLL is powered down, or when the differential reference input
is not selected. The single-ended buffers power down when the
PLL is powered down and when their individual power-down
registers are set. When the differential mode is selected, the
single-ended inputs are powered down.
In differential mode, the reference input pins are internally self-
biased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by a
single-ended signal, the unused side (REFIN) should be decoupled
via a suitable capacitor to a quiet ground.
shows the
equivalent circuit of REFIN.
VS
REF1
REF2
REFIN
150
10k
12k
10k
REFIN
85k
VS
85k
VS
0
7972
-06
6
Figure 37. REFIN Equivalent Circuit
Reference Switchover
The AD9516 supports dual single-ended CMOS inputs, as well as
a single differential reference input. In dual single-ended reference
mode, automatic and manual PLL reference clock switching
between REF1 (Pin REFIN) and REF2 (Pin REFIN) is supported.
This feature supports networking and other applications that
require smooth switching of redundant references. When used in
conjunction with the automatic holdover function, the
can achieve a worst-case reference input switchover with an
output frequency disturbance as low as 10 ppm.
When using reference switchover, the single-ended reference inputs
should be dc-coupled CMOS levels that are never allowed to go to
high impedance. If the inputs are allowed to go to high impedance,
noise may cause the buffer to chatter, causing false detection of
the presence of a reference. Reference switchover can be performed
manually or automatically. Manual switchover is performed
either through Register 0x01C or by using the REF_SEL pin.
Manual switchover requires the presence of a clock on the reference
input that is being switched to, or that the deglitching feature be
disabled (Register 0x01C[7]). The reference switching logic fails
if this condition is not met, and the PLL does not reacquire.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9516-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN W/PLL 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9516-5PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator |
| AD9517-0A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9517-0A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9517-0ABCPZ | 功能描述:IC CLOCK GEN 2.8GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9517-0ABCPZ-RL7 | 功能描述:IC CLOCK GEN 2.8GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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