參數(shù)資料
型號: AD9516-5BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 3/76頁
文件大?。?/td> 0K
描述: IC CLOCK GEN W/PLL 64-LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:14
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
AD9516-5
Rev. A | Page 11 of 76
LD, STATUS, AND REFMON PINS
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs; see
Table 49: Register 0x017, Register 0x01A, and Register 0x01B
Output Voltage High, VOH
2.7
V
Output Voltage Low, VOL
0.4
V
MAXIMUM TOGGLE RATE
100
MHz
Applies when mux is set to any divider or counter output or
PFD up/down pulse; also applies in analog lock detect mode;
usually debug mode only; beware that spurs may couple to
output when any of these pins are toggling
ANALOG LOCK DETECT
Capacitance
3
pF
On-chip capacitance; used to calculate RC time constant for
analog lock detect readback; use a pull-up resistor
REF1, REF2, AND CLK FREQUENCY STATUS
MONITOR
Normal Range
1.02
MHz
Frequency above which the monitor always indicates the
presence of the reference
Extended Range
8
kHz
Frequency above which the monitor always indicates the
presence of the reference
LD PIN COMPARATOR
Trip Point
1.6
V
Hysteresis
260
mV
POWER DISSIPATION
Table 13.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER DISSIPATION, CHIP
The values in this table include all power supplies, unless
otherwise noted; the power deltas for individual drivers are
at dc; see Figure 7, Figure 8, and Figure 9 for power dissipation
vs. output frequency
Power-On Default
1.0
1.2
W
No clock; no programming; default register values; does not
include power dissipated in external resistors; this configuration
has the following blocks already powered up: VCO divider,
six channel dividers, three LVPECL drivers, and two LVDS drivers
Full Operation; CMOS Outputs at 225 MHz
1.5
2.1
W
fCLK = 2.25 GHz; VCO divider = 2; all channel dividers on; six
LVPECL outputs at 562.5 MHz; eight CMOS outputs (10 pF load)
at 225 MHz; all four fine delay blocks on, maximum current;
does not include power dissipated in external resistors
Full Operation; LVDS Outputs at 225 MHz
1.5
2.1
W
fCLK = 2.25 GHz; VCO divider = 2; all channel dividers on; six
LVPECL outputs at 562.5 MHz; four LVDS outputs at 225 MHz;
all four fine delay blocks on: maximum current; does not include
power dissipated in external resistors
PD Power-Down
75
185
mW
PD pin pulled low; does not include power dissipated in
terminations
PD Power-Down, Maximum Sleep
31
mW
PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
SYNC power-down, Register 0x230[2] = 1b; REF for distribution
power-down, Register 0x230[1] = 1b
VCP Supply
4
4.8
mW
PLL operating; typical closed-loop configuration (this
number is included in all other power measurements)
220
mW
AD9516 core only, all drivers off, PLL off, VCO divider off, and
delay blocks off; the power consumption of the configuration
of the user can be derived from this number and the power
deltas that follow
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