參數(shù)資料
型號(hào)： AD9512/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/48頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9512
設(shè)計(jì)資源： AD9512 Eval Brd BOM
AD9511/12 All Layers
AD9511/12 Schematics
AD9511/12 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘分配
已用 IC / 零件： AD9512
已供物品： 板
AD9512
Rev. A | Page 10 of 48
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK1 = 622.08 MHz
40
fs rms
BW = 12 kHz 20 MHz (OC-12)
Any LVPECL (OUT0 to OUT2) = 622.08 MHz
Divide Ratio = 1
CLK1 = 622.08 MHz
55
fs rms
BW = 12 kHz 20 MHz (OC-3)
Any LVPECL (OUT0 to OUT2) = 155.52 MHz
Divide Ratio = 4
CLK1 = 400 MHz
215
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
215
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 100 MHz
Interferer(s)
Both LVDS (OUT3, OUT4) = 100 MHz
Interferer(s)
CLK1 = 400 MHz
222
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Interferer(s)
Both LVDS (OUT3, OUT4) = 50 MHz
Interferer(s)
CLK1 = 400 MHz
225
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Interferer(s)
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off)
Interferer(s)
CLK1 = 400 MHz
225
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Interferer(s)
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On)
Interferer(s)
LVDS OUTPUT ADDITIVE TIME JITTER
CLK1 = 400 MHz
264
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
319
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
395
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
LVDS (OUT4) = 50 MHz
Interferer(s)
All LVPECL = 50 MHz
Interferer(s)
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