參數(shù)資料
型號(hào)： AD9510-VCO/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 46/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9510
設(shè)計(jì)資源： AD9510 Eval Brd BOM
AD9510 Eval Brd Schematics
AD9510 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘分配
已用 IC / 零件： AD9510
已供物品： 板
相關(guān)產(chǎn)品： AD9510BCPZ-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
AD9510BCPZ-REEL7-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
AD9510
Data Sheet
Rev. B | Page 50 of 56
Reg.
Addr.
(Hex) Bit(s) Name
Description
3C
[7:4]
Not used.
3D
3E
3F
40
[0]
Power-down
Power-down bit for both output and LVDS driver. 0 = LVDS/CMOS on (default), 1 = LVDS/CMOS power-down.
41
LVDS/CMOS
42
OUT4
43
OUT5
OUT6
OUT7
40
[2:1] Output current
level
41
LVDS
42
OUT4
43
OUT5
OUT6
OUT7
[2]
[1]
Current (mA)
Termination (Ω)
0
1.75
100
0
1
3.5 (default)
100
1
0
5.25
50
1
7
50
40
[3]
LVDS/CMOS select 0 = LVDS (default), 1 = CMOS.
41
OUT4
42
OUT5
43
OUT6
OUT7
[4]
Inverted CMOS
driver
Effects output only when in CMOS mode.
0 = disable inverted CMOS driver (default), 1 = enable inverted CMOS driver.
40
OUT4
41
OUT5
42
OUT6
43
OUT7
40
[7:5]
Not used.
41
42
43
44
[7:0]
Not used.
45
[0]
Clock select
0: CLK2 drives distribution section, 1: CLK1 drives distribution section (default).
45
[1]
CLK1 power-down 1 = CLK1 input is powered down (default = 0b).
45
[2]
CLK2 power-down 1 = CLK2 input is powered down (default = 0b).
45
[3]
Prescaler clock
power-down
1 = shut down clock signal to PLL prescaler (default = 0b).
45
[4]
REFIN power-down 1 = power-down REFIN (default = 0b).
45
[5]
All clock inputs
power-down
1 = power-down CLK1 and CLK2 inputs and associated bias and internal clock tree (default = 0b).
45
[7:6]
Not used.
46
[7:0]
Not used.
47
[7:0]
Not used.
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