參數(shù)資料
型號(hào)： AD9510-VCO/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/56頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR AD9510
設(shè)計(jì)資源： AD9510 Eval Brd BOM
AD9510 Eval Brd Schematics
AD9510 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘分配
已用 IC / 零件： AD9510
已供物品： 板
相關(guān)產(chǎn)品： AD9510BCPZ-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
AD9510BCPZ-REEL7-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
Data Sheet
AD9510
Rev. B | Page 39 of 56
SINGLE-CHIP SYNCHRONIZATION
SYNCB—Hardware SYNC
The AD9510 clocks can be synchronized to each other at any
time. The outputs of the clocks are forced into a known state
with respect to each other and then allowed to continue clocking
from that state in synchronicity. Before a synchronization is
done, the FUNCTION Pin must be set to act as the SYNCB:
Register 0x58[6:5] = 01b input (Register 0x58[6:5] = 01b).
Synchronization is done by forcing the FUNCTION pin low,
creating a SYNCB signal and then releasing it.
See the SYNCB: Register 0x58[6:5] = 01b section for a more
detailed description of what happens when the SYNCB:
Register 0x58[6:5] = 01b signal is issued.
Soft SYNC—Register 0x58[2]
A soft SYNC can be issued by means of a bit in Registers 0x58[2].
This soft SYNC works the same as the SYNCB, except that the
polarity is reversed. A 1 written to this bit forces the clock outputs
into a known state with respect to each other. When a 0 is
subsequently written to this bit, the clock outputs continue
clocking from that state in synchronicity.
MULTICHIP SYNCHRONIZATION
The AD9510 provides a means of synchronizing two or more
AD9510s. This is not an active synchronization; it requires user
monitoring and action. The arrangement of two AD9510s to be
synchronized is shown in Figure 43.
Synchronization of two or more AD9510s requires a fast clock
and a slow clock. The fast clock can be up to 1 GHz and can be
the clock driving the master AD9510 CLK1 input or one of the
outputs of the master. The fast clock acts as the input to the
distribution section of the slave AD9510 and is connected to its
CLK1 input. The PLL can be used on the master, but the slave
PLL is not used.
The slow clock is the clock that is synchronized across the two
chips. This clock must be no faster than one-fourth of the fast
clock, and no greater than 250 MHz. The slow clock is taken
from one of the outputs of the master AD9510 and acts as the
REFIN (or CLK2) input to the slave AD9510. One of the outputs
of the slave must provide this same frequency back to the CLK2
(or REFIN) input of the slave.
Multichip synchronization is enabled by writing
Register 0x58[0] = 1 on the slave AD9510. When this bit is set,
the STATUS pin becomes the output for the SYNC signal. A low
signal indicates an in-sync condition, and a high indicates an
out-of-sync condition.
Register 0x58[1] selects the number of fast clock cycles that are
the maximum separation of the slow clock edges that are con-
sidered synchronized. When Register 0x58[1] = 0 (default), the
slow clock edges must be coincident within 1 to 1.5 high speed
clock cycles. If the coincidence of the slow clock edges is closer
than this amount, the SYNC flag stays low. If the coincidence of
the slow clock edges is greater than this amount, the SYNC flag
is set high. When Register 0x58[1] = 1b, the amount of coincidence
required is 0.5 fast clock cycles to 1 fast clock cycles.
Whenever the SYNC flag is set high, indicating an out-of-sync
condition, a SYNCB signal applied simultaneously at the
FUNCTION pins of both AD9510s brings the slow clocks into
synchronization.
Figure 43. Multichip Synchronization
05046-039
AD9510
MASTER
FAST CLOCK
<1GHz
SLOW CLOCK
<250MHz
AD9510
SLAVE
FAST CLOCK
<1GHz
SLOW
CLOCK
<250MHz
SYNC
DETECT
CLK2
REFIN
OUTY
OUTM
OUTN
FSYNC
STATUS
(SYNC)
FUNCTION
(SYNCB)
FUNCTION
(SYNCB)
SYNCB
CLK1
相關(guān)PDF資料
PDF描述
RBM22DSUI CONN EDGECARD 44POS DIP .156 SLD
A2MXS-2406M ADM24S/AE24M/X
MLF1608A1R5J INDUCTOR MULTILAYER 1.5UH 0603
RCM22DCTI CONN EDGECARD 44POS DIP .156 SLD
Q5-2X-1/8-01-QB48IN-25 HEATSHRK DL WALL Q52X 1/8"X4'BLK
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9511 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9511/PCB 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk
AD9511BCPZ 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
AD9511BCPZ-REEL 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9511BCPZ-REEL7 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*