參數(shù)資料
型號(hào)： AD9510-VCO/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 41/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9510
設(shè)計(jì)資源： AD9510 Eval Brd BOM
AD9510 Eval Brd Schematics
AD9510 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘分配
已用 IC / 零件： AD9510
已供物品： 板
相關(guān)產(chǎn)品： AD9510BCPZ-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
AD9510BCPZ-REEL7-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
AD9510
Data Sheet
Rev. B | Page 46 of 56
REGISTER MAP DESCRIPTION
Table 25 lists the AD9510 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by square
brackets. For example, [3] refers to Bit 3, while [5:2] refers to the range of bits from Bit 5 through Bit 2. Table 25 describes the
functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 24.
Table 25. AD9510 Register Descriptions
Reg.
Addr.
(Hex) Bit(s) Name
Description
Serial control port
configuration
Any changes to this register take effect immediately. Register 0x5A[0] update registers does not have to
be written.
00
[3:0]
Not used.
00
[4]
Long instruction
When this bit is set (1), the instruction phase is 16 bits. When this bit is clear (0), the instruction phase is
8 bits. The default, and only, mode for this part is long instruction (default = 1b).
00
[5]
Soft reset
When this bit is set (1), the chip executes a soft reset, restoring default values to the internal registers, except for
this register, Register 0x00. This bit is not self-clearing. A clear (0) must be written to it to clear it.
00
[6]
LSB_FIRST
When this bit is set (1), the input and output data is oriented as LSB first. Additionally, register addressing
increments. If this bit is clear (0), data is oriented as MSB first and register addressing decrements
(default = 0b, MSB first)
00
[7]
SDO inactive
(bidirectional
mode)
When set (1), the SDO pin is tristate and all read data goes to the SDIO pin. When clear (0), the SDO is
active (unidirectional mode) (default = 0b).
Not used
01
[7:0]
Not used.
02
[7:0]
Not used.
03
[7:0]
Not used.
PLL settings
04
[5:0] A counter
6-bit A counter[5:0].
04
[7:6]
Not used.
05
[4:0] B counter MSBs
13-bit B counter MSB[12:8].
05
[7:5]
Not used.
06
[7:0] B counter LSBs
13-bit B counter LSB[7:0].
07
[1:0]
Not used.
07
[2]
LOR enable
1 = enables the loss of reference (LOR) function (default = 0b).
07
[4:3]
Not used.
07
[6:5] LOR initial lock
detect delay
LOR initial lock detect delay. Once a lock detect is indicated, this is the number of phase frequency
detector (PFD) cycles that occur prior to turning on the LOR monitor.
[6]
[5]
LOR Initial Lock Detect Delay
0
3 PFD cycles (default)
0
1
6 PFD cycles
1
0
12 PFD cycles
1
24 PFD cycles
07
[7]
Not used.
08
[1:0] Charge pump mode
[1]
[0]
Charge Pump Mode
0
Tristated (default)
0
1
Pump-up
1
0
Pump-down
1
Normal operation
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