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參數(shù)資料
| 型號： | AD9510-VCO/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9510 |
| 設(shè)計(jì)資源： | AD9510 Eval Brd BOM AD9510 Eval Brd Schematics AD9510 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘分配 |
| 已用 IC / 零件： | AD9510 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9510BCPZ-ND - IC CLOCK DIST 8OUT PLL 64LFCSP AD9510BCPZ-REEL7-ND - IC CLOCK DIST 8OUT PLL 64LFCSP |
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Data Sheet
AD9510
Rev. B | Page 3 of 56
5/05—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Table 1 and Table 2 .......................................................5
Changes to Table 4 ............................................................................8
Changes to Table 5 ............................................................................9
Changes to Table 6 ..........................................................................14
Changes to Table 8 and Table 9 .....................................................15
Changes to Table 11 ........................................................................16
Changes to Table 13 ........................................................................20
Changes to Figure 7 and Figure 10 ...............................................22
Changes to Figure 19 to Figure 23 ................................................24
Changes to Figure 30 and Figure 31 .............................................26
Changes to Figure 32 ......................................................................27
Changes to Figure 33 ......................................................................28
Changes to VCO/VCXO Clock Input—CLK2 Section..............29
Changes to A and B Counters Section .........................................30
Changes to PLL Digital Lock Detect Section ..............................31
Changes to PLL Analog Lock Detect Section..............................32
Changes to Loss of Reference Section ..........................................32
Changes to FUNCTION Pin Section ...........................................33
Changes to RESETB: 58h<6:5> = 00b (Default) Section ...........33
Changes to SYNCB: 58h<6:5> = 01b Section..............................33
Changes to CLK1 and CLK2 Clock Inputs Section....................33
Changes to Calculating the Delay Section...................................38
Changes to Soft Reset via the Serial Port Section.......................41
Changes to Multichip Synchronization Section..........................41
Changes to Serial Control Port Section .......................................42
Changes to Serial Control Port Pin Descriptions Section .........42
Changes to General Operation of Serial
Control Port Section.......................................................................42
Added Framing a Communication Cycle with CSB Section ....42
Added Communication Cycle—Instruction Plus
Data Section.....................................................................................42
Changes to Write Section...............................................................42
Changes to Read Section................................................................42
Changes to The Instruction Word (16 Bits) Section ..................43
Changes to Table 20 ........................................................................43
Changes to MSB/LSB First Transfers Section .............................43
Changes to Table 21 ........................................................................44
Added Figure 52; Renumbered Sequentially...............................45
Changes to Table 23 ........................................................................46
Changes to Table 24 ........................................................................49
Changes to Using the AD9510 Outputs for ADC Clock
Applications .....................................................................................57
4/05—Revision 0: Initial Version
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9511 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511/PCB | 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9511BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9511BCPZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511BCPZ-REEL7 | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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