參數(shù)資料
型號(hào)： AD9510-VCO/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 3/56頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9510
設(shè)計(jì)資源： AD9510 Eval Brd BOM
AD9510 Eval Brd Schematics
AD9510 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘分配
已用 IC / 零件： AD9510
已供物品： 板
相關(guān)產(chǎn)品： AD9510BCPZ-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
AD9510BCPZ-REEL7-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
Data Sheet
AD9510
Rev. B | Page 11 of 56
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 622.08 MHz
40
fs rms
Bandwidth = 12 kHz 20 MHz (OC-12)
Any LVPECL (OUT0 to OUT3) = 622.08 MHz
Divide Ratio = 1
CLK1 = 622.08 MHz
55
fs rms
Bandwidth = 12 kHz 20 MHz (OC-3)
Any LVPECL (OUT0 to OUT3) = 155.52 MHz
Divide Ratio = 4
CLK1 = 400 MHz
215
fs rms
Calculated from signal-to-noise ratio (SNR) of
ADC method, fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
215
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 100 MHz
Interferer(s)
All LVDS (OUT4 to OUT7) = 100 MHz
Interferer(s)
CLK1 = 400 MHz
222
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
Interferer(s)
All LVDS (OUT4 to OUT7) = 50 MHz
Interferer(s)
CLK1 = 400 MHz
225
fs rms
Calculated from SNR of ADC method;
fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
Interferer(s)
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs Off)
Interferer(s)
CLK1 = 400 MHz
225
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
Interferer(s)
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs On)
Interferer(s)
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 400 MHz
264
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
319
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4
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