AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f
參數(shù)資料
型號(hào): AD9272BSVZRL-65
廠商: Analog Devices Inc
文件頁(yè)數(shù): 43/44頁(yè)
文件大?。?/td> 0K
描述: IC ADC ASD OCTAL 65MSPS 100-TQFP
設(shè)計(jì)資源: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
標(biāo)準(zhǔn)包裝: 1,000
類型: AAF,ADC,交叉點(diǎn)開關(guān),LNA,VGA
分辨率(位): 12 b
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 1.8V,3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
配用: AD9272-65EBZ-ND - BOARD EVAL AD9272
AD9272
Rev. C | Page 8 of 44
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 2.
Parameter1
Temperature
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
250
mV p-p
Input Common-Mode Voltage
Full
1.2
V
Input Resistance (Differential)
25°C
20
Input Capacitance
25°C
1.5
pF
LOGIC INPUTS (PDWN, STBY, SCLK)
Logic 1 Voltage
Full
1.2
3.6
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
30
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
3.6
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
70
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (SDIO)
Logic 1 Voltage
Full
1.2
DRVDD + 0.3
V
Logic 0 Voltage
Full
0
0.3
V
Input Resistance
25°C
30
Input Capacitance
25°C
2
pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Full
1.79
V
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
DIGITAL OUTPUTS (DOUTx+, DOUTx), IN ANSI-644 MODE1
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
454
mV
Output Offset Voltage (VOS)
Full
1.125
1.375
V
Output Coding (Default)
Offset binary
DIGITAL OUTPUTS (DOUTx+, DOUTx), WITH
LOW POWER, REDUCED SIGNAL OPTION1
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
250
mV
Output Offset Voltage (VOS)
Full
1.10
1.30
V
Output Coding (Default)
Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
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