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參數(shù)資料
| 型號(hào)： | AD9272BSVZRL-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC ASD OCTAL 65MSPS 100-TQFP |
| 設(shè)計(jì)資源： | Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | AAF，ADC，交叉點(diǎn)開關(guān)，LNA，VGA |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.8V，3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9272-65EBZ-ND - BOARD EVAL AD9272 |
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AD9272
Rev. C | Page 35 of 44
600
–400
400
–200
200
–600
0
–1.5ns
–0.5ns
–1.0ns
0ns
0.5ns
1.0ns
1.5ns
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EYE: ALL BITS
ULS: 2396/2396
25
0
5
10
15
20
–200ps
–100ps
0ps
100ps
200ps
TI
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J
ITT
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37
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 11.
To change the output data format to twos complement, see the
Memory Map section.
Table 11. Digital Output Coding
Code
(VIN+) (VIN),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D11...D0)
4095
+1.00
1111 1111 1111
2048
0.00
1000 0000 0000
2047
0.000488
0111 1111 1111
0
1.00
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 960 Mbps
(12 bits × 80 MSPS = 960 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required for
a specific application. See Table 17 for details on enabling this
feature.
Two output clocks are provided to assist in capturing data from
the AD9272. DCO± is used to clock the output data and is equal
to six times the sampling clock rate. Data is clocked out of the
AD9272 and must be captured on the rising and falling edges of
the DCO± that supports double data rate (DDR) capturing. The
frame clock output (FCO±) is used to signal the start of a new
output byte and is equal to the sampling clock rate. See the
timing diagram shown in Figure 2 for more information.
Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4
Table 12. Flexible Output Test Modes
Output Test Mode
Bit Sequence
Pattern Name
Digital Output Word 1
Digital Output Word 2
Subject to Data
Format Select
0000
Off (default)
N/A
0001
Midscale short
1000 0000 0000
Yes
0010
+Full-scale short
1111 1111 1111
Yes
0011
Full-scale short
0000 0000 0000
Yes
0100
Checkerboard output
1010 1010 1010
0101 0101 0101
No
0101
PN sequence long
N/A
Yes
0110
PN sequence short
N/A
Yes
0111
One-/zero-word toggle
1111 1111 1111
0000 0000 0000
No
1000
User input
Register 0x19 to Register 0x1A
Register 0x1B to Register 0x1C
No
1001
1-/0-bit toggle
1010 1010 1010
N/A
No
1010
1× sync
0000 0011 1111
N/A
No
1011
One bit high
1000 0000 0000
N/A
No
1100
Mixed bit frequency
1010 0011 0011
N/A
No
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| AD9272BSVZRL-651 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9272BSVZRL-80 | 功能描述:IC ADC ASD OCTAL 80MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD9272BSVZRL-801 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9273 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9273_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
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