參數(shù)資料
型號(hào)： AD9272BSVZRL-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/44頁(yè)
文件大?。?/td> 0K
描述： IC ADC ASD OCTAL 65MSPS 100-TQFP
設(shè)計(jì)資源： Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
標(biāo)準(zhǔn)包裝： 1,000
類型： AAF，ADC，交叉點(diǎn)開關(guān)，LNA，VGA
分辨率（位）： 12 b
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行
電壓電源： 模擬和數(shù)字
電源電壓： 1.8V，3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
配用： AD9272-65EBZ-ND - BOARD EVAL AD9272
AD9272
Rev. C | Page 28 of 44
Table 9. Sensitivity and Dynamic Range of Trade-Offs1, 2, 3
LNA
VGA
Channel
Gain
Full-Scale Input
(V p-p)
Input-Referred
Noise Voltage
(nV/√Hz)
Postamp Gain (dB)
Typical Output Dynamic Range
Input-Referred Noise4 @
GAIN+ = 1.6 V (nV/√Hz)
(V/V)
(dB)
GAIN+ = 0 V5
GAIN+ = 1.6 V6
6
15.6
0.733
0.98
21
67.5
65.1
1.395
24
66.4
63.0
1.286
27
64.6
60.6
1.227
30
62.5
57.9
1.197
8
17.9
0.550
0.86
21
67.5
64.5
1.149
24
66.4
62.3
1.071
27
64.5
59.8
1.030
30
62.5
57.1
1.009
12
21.3
0.367
0.75
21
67.5
63.3
0.910
24
66.4
60.9
0.865
27
64.6
58.2
0.842
30
62.5
55.4
0.830
1 LNA: output full scale = 4.4 V p-p differential.
2 Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN = 0.8 V.
3 ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input.
4 Channel noise at maximum VGA gain.
5 Output dynamic range at minimum VGA gain (VGA dominated).
6 Output dynamic range at maximum VGA gain (LNA dominated).
Table 9 demonstrates the sensitivity and dynamic range of
trade-offs that can be achieved relative to various LNA and
VGA gain settings.
For example, when the VGA is set for the minimum gain voltage,
the TGC path is dominated by VGA noise and achieves the
maximum output SNR. However, as the postamp gain options
are increased, the input-referred noise is reduced, and the SNR
is degraded.
If the VGA is set for the maximum gain voltage, the TGC path
is dominated by LNA noise and achieves the lowest input-
referred noise but with degraded output SNR. The higher the
TGC (LNA + VGC) gain, the lower the output SNR. As the
postamp gain is increased, the input-referred noise is reduced.
At low gains, the VGA should limit the system noise perfor-
mance (SNR); at high gains, the noise is defined by the source and
the LNA. The maximum voltage swing is bound by the full-
scale peak-to-peak ADC input voltage (2 V p-p).
Both the LNA and VGA have full-scale limitations within each
section of the TGC path. These limitations are dependent on the
gain setting of each function block and on the voltage applied to the
GAIN± pins. The LNA has three limitations, or full-scale settings,
that can be applied through the SPI. Similarly, the VGA has four
postamp gain settings that can be applied through the SPI. The
voltage applied to the GAIN± pins determines which amplifier
(the LNA or VGA) saturates first. The maximum signal input level
that can be applied as a function of voltage on the GAIN± pins
for the selectable gain options of the SPI is shown in Figure 47 to
0
0.1
0.2
0.3
0.4
0.5
0.6
0.8
0.7
0.9
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
IN
P
U
T
FU
L
S
C
A
L
E
(
V
p-
p)
GAIN+ (V)
07
02
9-
1
77
PGA GAIN = 21dB
PGA GAIN = 24dB
PGA GAIN = 27dB
PGA GAIN = 30dB
Figure 47. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations
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