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參數(shù)資料
| 型號： | AD9272BSVZRL-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC ASD OCTAL 65MSPS 100-TQFP |
| 設(shè)計資源： | Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135) |
| 標準包裝： | 1,000 |
| 類型： | AAF，ADC，交叉點開關(guān)，LNA，VGA |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.8V，3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9272-65EBZ-ND - BOARD EVAL AD9272 |
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AD9272
Rev. C | Page 42 of 44
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
Default Notes/
Comments
0F
Flex_channel_input
Filter cutoff frequency control
0000 = 1.3 × 1/3 × fSAMPLE
0001 = 1.2 × 1/3 × fSAMPLE
0010 = 1.1 × 1/3 × fSAMPLE
0011 = 1.0 × 1/3 × fSAMPLE (default)
0100 = 0.9 × 1/3 × fSAMPLE
0101 = 0.8 × 1/3 × fSAMPLE
0110 = 0.7 × 1/3 × fSAMPLE
1000 = 1.3 × 1/4.5 × fSAMPLE
1001 = 1.2 × 1/4.5 × fSAMPLE
1010 = 1.1 × 1/4.5 × fSAMPLE
1011 = 1.0 × 1/4.5 × fSAMPLE
1100 = 0.9 × 1/4.5 × fSAMPLE
1101 = 0.8 × 1/4.5 × fSAMPLE
1110 = 0.7 × 1/4.5 × fSAMPLE
X
0x30
Antialiasing filter
cutoff (global).
10
Flex_offset
X
6-bit LNA offset adjustment
10 0000 for LNA bias high, mid-high, mid-low (default)
10 0001 for LNA bias low
0x20
LNA force offset
correction
(local).
11
Flex_gain
X
PGA gain
00 = 21 dB
01 = 24 dB (default)
10 = 27 dB
11 = 30 dB
LNA gain
00 = 15.6 dB
01 = 17.9 dB
10 = 21.3 dB
(default)
0x06
LNA and PGA
gain adjustment
(global).
12
Bias_current
X
1
X
LNA bias
00 = high (default)
01 = mid-high
10 = mid-low
11 = low
0x08
LNA bias current
adjustment
(global).
14
Output_mode
X
0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE
1596.3
similar)
X
Output
invert
1 = on
0 = off
(default)
00 = offset binary
(default)
01 = twos
complement
0x00
Configures the
outputs and the
format of the data
(Bits[7:3] and
Bits[1:0] are global;
Bit 2 is local).
15
Output_adjust
X
Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X
DCO±
and
FCO±
2× drive
strength
1 = on
0 = off
(default)
0x00
Determines LVDS
or other output
properties.
Primarily functions
to set the LVDS
span and
common-mode
levels in place of
an external resistor
(Bits[7:1] are global;
Bit 0 is local).
16
Output_phase
X
0011 = output clock phase adjust
(0000 through 1010)
(Default: 180° relative to data edge)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge
0100 = 240° relative to data edge
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = 420° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03
On devices that
use global clock
divide,
determines which
phase of the
divider output is
used to supply
the output clock.
Internal latching
is unaffected.
18
Flex_vref
X
0 =
internal
reference
1 =
external
reference
X
0x00
Select internal
reference
(recommended
default) or
external
reference
(global).
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| AD9272BSVZRL-651 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9272BSVZRL-80 | 功能描述:IC ADC ASD OCTAL 80MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
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