參數(shù)資料
型號： AD9239BCPZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 31/40頁
文件大小： 0K
描述： IC ADC 12BIT DUAL 170MSPS 72PIN
標準包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.22W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 托盤
輸入數(shù)目和類型： 8 個單端，單極；4 個差分，單極
Data Sheet
AD9239
Rev. C | Page 37 of 40
Power and Ground Recommendations
When connecting power to the AD9239, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the printed circuit board (PCB) level and close to the
parts, with minimal trace lengths.
A single PCB ground plane should be sufficient when using the
AD9239. With proper decoupling and smart partitioning of the
analog, digital, and clock sections of the PCB, optimum
performance can easily be achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC is connected to analog ground (AGND) to achieve the best
electrical and thermal performance of the AD9239. An exposed
continuous copper plane on the PCB should mate to the AD9239
exposed paddle, Pin 0. The copper plane should have several vias
to achieve the lowest possible resistive thermal path for heat
dissipation to flow through the bottom of the PCB. These vias
should be solder-filled or plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
guarantees only one tie point. See Figure 79 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the AN-772 Application Note,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP), at www.analog.com.
SILKSCREEN PARTITION
PIN 1 INDICATOR
06980-
029
Figure 79. Typical PCB Layout
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