參數(shù)資料
型號(hào)： AD9239BCPZ-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/40頁(yè)
文件大小： 0K
描述： IC ADC 12BIT DUAL 170MSPS 72PIN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.22W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；4 個(gè)差分，單極
Data Sheet
AD9239
Rev. C | Page 33 of 40
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map register table (Table 15) has eight
bit locations. The memory map is divided into three sections: the
chip configuration registers (Address 0x00 to Address 0x02), the
device index and transfer registers (Address 0x05 and
Address 0xFF), and the ADC functions registers (Address 0x08 to
Address 0x53).
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The Bit 7 column is the start of the default
hexadecimal value given. For example, Address 0x09, the clock
register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6
= 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and
Bit 0 = 1, or 0000 0001 in binary. This setting is the default for
the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0
of this address, followed by a 0x01 in Register 0xFF (transfer bit),
the duty cycle stabilizer turns off. It is important to follow each
writing sequence with a transfer bit to update the SPI registers. For
more information on this and other functions, consult the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
When the AD9239 comes out of a reset, critical registers are
preloaded with default values. These values are indicated in
Table 15, where an X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
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