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參數(shù)資料
型號(hào)： AD9239BCPZ-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/40頁(yè)
文件大小： 0K
描述： IC ADC 12BIT DUAL 170MSPS 72PIN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.22W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；4 個(gè)差分，單極
AD9239
Data Sheet
Rev. C | Page 26 of 40
Scramblers
There are three scramblers on the AD9239. The scramblers are
an Ethernet scrambler (x58 + x39 + 1), a SONET scrambler (x7 +
x6 + 1), and a static inverter scrambler (inverts bits at set locations
in the packet). The scramblers are used to help balance the number
of 1s and 0s in the packet.
The Ethernet and SONET scramblers work on scrambling the
whole packet (64 bits), the header and the data (56 bits), or just
the data (48 bits). The scrambler is self-synchronizing on the
descramble end or receive end and does not require an additional
sync bit. For a copy of either the Ethernet or SONET scrambler
code, send an email to highspeed.converters@analog.com.
Figure 65 and Figure 66 show the serial implementation of the
Ethernet and SONET scramblers. The parallel implementation
allows the scrambler and descrambler to run at a slower clock
rate and can be implemented in the fabric of a receiver.
The serial implementations of the Ethernet and SONET scramblers
more easily show what is being done. The parallel implementation
must be derived from the serial implementation. The end product
depends on how many bits need to be processed in parallel. For
the scrambler, 64 bits are processed even in the 56- and 48-bit
cases. To achieve this for 56 bits and 48 bits, a portion of two
samples is used to fill the rest of the input word.
Inverter Balance Example
The inverter implementation uses predetermined bit positions
to balance the packet in an overrange condition (all 1s or all 0s)
in the converter. The inversions are present in all conditions,
not just the overrange condition.
The descrambler can be based off any number of bits the user
chooses to process. In the inverter-based scrambler, the packet
is balanced based on an overranged condition. If each packet is
balanced, the bit stream should be balanced. Instead of a random
sequence that changes from packet to packet, certain inverts are
set at predetermined bit positions within the packet. This allows
the decoding to be done in the receiver end. Figure 67 shows the
inverters in the packet for the 12-bit data case and the inverter
order in the header.
Table 12 shows the average value of the packet for various
conditions.
Table 12. Average of 1s and 0s in Overrange Conditions
Assuming Header Bits are All 0
12-Bit
ECC
No Scramble (Data = 0)
0
00000000
No Scramble (Data = 1)
0.844
00111111
Average of Negative and Positive
Overrange
0.422
Scramble Only Data (Data = 0)
0.375
00000000
Scramble Only Data (Data = 1)
0.469
00111111
Average of Negative and Positive
Overrange
0.422
Scramble Data and Header (Data = 0)
0.437
00000000
Scramble Data and Header (Data = 1)
0.531
00111111
Average of Negative and Positive
Overrange
0.484
If the analog signal is out of range, there should be about the same
number of out-of-range positive and out-of-range negative values.
The average for no scrambling and for scrambling just the data
is about the same. If the header is used to indicate out of range,
the balance improves for the 12-bit case.
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