參數(shù)資料
型號(hào)： AD9239BCPZ-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT DUAL 170MSPS 72PIN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.22W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
AD9239
Data Sheet
Rev. C | Page 22 of 40
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9239.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note, the AN-756 Application
Note, and the Analog Dialogue article “Analog-to-Digital Converter
Clock Optimization: A Test Engineering Perspective” (Volume 42,
Number 2, February 2008) for more in-depth information about
jitter performance as it relates to ADCs (visit www.analog.com).
1
10
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16 BITS
14 BITS
12 BITS
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0.125 ps
0.25 ps
0.5 ps
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ANALOG INPUT FREQUENCY (MHz)
10 BITS
RMS CLOCK JITTER REQUIREMENT
S
NR
(
d
B)
06980-
024
Figure 57. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation
As shown in Figure 58 to Figure 60, the power dissipated by the
AD9239 is proportional to its clock rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the digital
output drivers.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
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0.2
0
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0.2
0.1
0
50
90
70
110
130
150
170
ENCODE (MSPS)
PO
W
ER
(W
)
CURRE
NT
(
mA)
06980-
056
IAVDD
POWER
IDRVDD
Figure 58. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 170 MSPS
2.0
1.8
1.6
1.4
1.2
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0
50
90
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190
210
ENCODE (MSPS)
PO
W
ER
(W
)
CURRE
NT
(
mA)
06980-
057
IAVDD
POWER
IDRVDD
Figure 59. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 210 MSPS
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
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50
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110
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190
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230
250
ENCODE (MSPS)
PO
W
ER
(W
)
CURRE
NT
(
mA)
06980-
058
IAVDD
POWER
IDRVDD
Figure 60. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 250 MSPS
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