參數(shù)資料
型號(hào)： AD9146BCPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/56頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT SRL DUAL 48LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： TxDAC+®
設(shè)置時(shí)間： 20ns
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 2 電流，單極
采樣率（每秒）： 1.23G
Data Sheet
AD9146
Rev. A | Page 35 of 56
COARSE MODULATION MIXING SEQUENCES
The coarse digital quadrature modulation occurs within the
interpolation filters. The modulation shifts the frequency
spectrum of the incoming data by the frequency offset selected.
The frequency offsets available are multiples of the input data
rate. The modulation is equivalent to multiplying the quadra-
ture input signal by a complex carrier signal, C(t), of the form
C(t) = cos(ωct) + j sin(ωct)
In practice, this modulation results in the mixing functions
Table 20. Modulation Mixing Sequences
Modulation
Mixing Sequence
fS/2
I = I, I, I, I, …
Q = Q, Q, Q, Q, …
fS/4
I = I, Q, I, Q, …
Q = Q, I, Q, I, …
3fS/4
I = I, Q, I, Q, …
Q = Q, I, Q, I, …
fS/8
I = I, r(I + Q), Q, r(I + Q), I, r(I + Q), Q, r(I Q), …
Q = Q, r(Q I), I, r(Q + I), Q, r(Q + I), I, r(Q + I), …
Note that
2
=
r
As shown in Table 20, the mixing functions of most of the modes
cross-couple samples between the I and Q channels. The I and
Q channels operate independently only in fS/2 mode. This
means that real modulation using both the I and Q DAC outputs
can only be done in fS/2 mode. All other modulation modes
require complex input data and produce complex output signals.
QUADRATURE PHASE CORRECTION
The purpose of the quadrature phase correction block is to
enable compensation of the phase imbalance of the analog
quadrature modulator following the DAC. If the quadrature
modulator has a phase imbalance, the unwanted sideband appears
with significant energy. Tuning the quadrature phase adjust value
can optimize image rejection in single sideband radios.
Ordinarily, the I and Q channels have an angle of precisely 90°
between them. The quadrature phase adjustment is used to change
the angle between the I and Q channels. When I Phase Adj[9:0]
(Register 0x38 and Register 0x39) is set to 1000000000, the I DAC
output moves approximately 1.75° away from the Q DAC output,
creating an angle of 91.75° between the channels. When I Phase
Adj[9:0] is set to 0111111111, the I DAC output moves approxi-
mately 1.75° toward the Q DAC output, creating an angle of
88.25° between the channels.
Q Phase Adj[9:0] (Register 0x3A and Register 0x3B) works in
a similar fashion. When Q Phase Adj[9:0] is set to 1000000000,
the Q DAC output moves approximately 1.75° away from the
I DAC output, creating an angle of 91.75° between the channels.
When Q Phase Adj[9:0] is set to 0111111111, the Q DAC output
moves approximately 1.75° toward the I DAC output, creating
an angle of 88.25° between the channels.
Based on these two endpoints, the combined resolution of the
phase compensation register is approximately 3.5°/1024 or
0.00342° per code.
DC OFFSET CORRECTION
The dc value of the I datapath and the Q datapath can be
independently controlled by adjusting the I DAC Offset[15:0]
and Q DAC Offset[15:0] values in Register 0x3C through
Register 0x3F. These values are added directly to the datapath
values. Care should be taken not to overrange the transmitted
values.
Figure 45 shows how the DAC offset current varies as a function
of the I DAC Offset[15:0] and Q DAC Offset[15:0] values. With
the digital inputs fixed at midscale (0x0000, twos complement data
format), Figure 45 shows the nominal IOUTxP and IOUTxN currents
as the DAC offset value is swept from 0 to 65,535. Because IOUTxP
and IOUTxN are complementary current outputs, the sum of IOUTxP
and IOUTxN is always 20 mA.
0x0000
0x4000
0x8000
0xC000
0xFFFF
5
10
15
20
5
10
15
20
0
DAC OFFSET VALUE
I O
UT
x
N
(mA)
I O
UT
x
P
(
mA)
09691-
050
Figure 45. DAC Output Currents vs. DAC Offset Value
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