參數(shù)資料
型號: AD9146BCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 18/56頁
文件大?。?/td> 0K
描述: IC DAC 16BIT SRL DUAL 48LFCSP
標(biāo)準(zhǔn)包裝: 2,500
系列: TxDAC+®
設(shè)置時間: 20ns
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-WQ(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 1.23G
Data Sheet
AD9146
Rev. A | Page 25 of 56
Register
Name
Address
(Hex)
Bits
Name
Description
Default
Datapath
Config
0x1E
0
Set to 1
Set this bit to 1 for proper operation. (The default value
must be changed from 0 to 1.)
0
Chip ID
0x1F
[7:0]
Chip ID[7:0]
This register identifies the device as an AD9146.
00001000
I Phase Adj
LSB
0x38
[7:0]
I Phase Adj[7:0]
See Register 0x39.
00000000
I Phase Adj
MSB
0x39
[1:0]
I Phase Adj[9:8]
I Phase Adj[9:0] is used to insert a phase offset between
the I and Q datapaths. This offset can be used to correct
for phase imbalance in a quadrature modulator. See the
Quadrature Phase Correction section for more information.
00
Q Phase Adj
LSB
0x3A
[7:0]
Q Phase Adj[7:0]
See Register 0x3B.
00000000
Q Phase Adj
MSB
0x3B
[1:0]
Q Phase Adj[9:8]
Q Phase Adj[9:0] is used to insert a phase offset between
the I and Q datapaths. This offset can be used to correct
for phase imbalance in a quadrature modulator. See the
Quadrature Phase Correction section for more information.
00
I DAC Offset
LSB
0x3C
[7:0]
I DAC Offset[7:0]
See Register 0x3D.
00000000
I DAC Offset
MSB
0x3D
[7:0]
I DAC Offset[15:8]
I DAC Offset[15:0] is a value that is added directly to the
samples written to the I DAC.
00000000
Q DAC
Offset LSB
0x3E
[7:0]
Q DAC Offset[7:0]
See Register 0x3F.
00000000
Q DAC
Offset MSB
0x3F
[7:0]
Q DAC Offset[15:8]
Q DAC Offset[15:0] is a value that is added directly to the
samples written to the Q DAC.
00000000
I DAC
FS Adjust
0x40
[7:0]
I DAC FS Adj[7:0]
See Register 0x41, Bits[1:0].
11111001
I DAC
Control
0x41
7
I DAC sleep
1 = puts the I DAC into sleep mode (fast wake-up mode).
0
[1:0]
I DAC FS Adj[9:8]
I DAC FS Adj[9:0] sets the full-scale current of the I DAC.
The full-scale current can be adjusted from 8.64 mA to
31.68 mA in step sizes of approximately 22.5 A.
01
0x000 = 8.64 mA.
0x200 = 20.16 mA.
0x3FF = 31.68 mA.
I Aux DAC
Data
0x42
[7:0]
I Aux DAC[7:0]
See Register 0x43, Bits[1:0].
00000000
I Aux DAC
Control
0x43
7
I aux DAC sign
0 = the I auxiliary DAC sign is positive, and the current is
directed to the IOUT1P pin (Pin 47).
0
1 = the I auxiliary DAC sign is negative, and the current is
directed to the IOUT1N pin (Pin 46).
6
I aux DAC current
direction
0 = the I auxiliary DAC sources current.
0
1 = the I auxiliary DAC sinks current.
5
I aux DAC sleep
1 = puts the I auxiliary DAC into sleep mode.
0
[1:0]
I Aux DAC[9:8]
I Aux DAC[9:0] sets the magnitude of the auxiliary DAC
current. The range is 0 mA to 2 mA, and the step size is 2 A.
00
0x000 = 0.000 mA.
0x001 = 0.002 mA.
0x3FF = 2.046 mA.
Q DAC
FS Adjust
0x44
[7:0]
Q DAC FS Adj[7:0]
See Register 0x45, Bits[1:0].
11111001
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