參數(shù)資料
型號(hào)： AD9146BCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 15/56頁
文件大小： 0K
描述： IC DAC 16BIT SRL DUAL 48LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： TxDAC+®
設(shè)置時(shí)間： 20ns
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 1.23G
AD9146
Data Sheet
Rev. A | Page 22 of 56
Register
Name
Address
(Hex)
Bits
Name
Description
Default
Clock
Receiver
Control
0x08
7
DACCLK duty correction
1 = enable duty cycle correction on the DACCLK input.
0
6
REFCLK duty correction
1 = enable duty cycle correction on the REFCLK input.
0
5
DACCLK cross-correction
1 = enable differential crossing correction on the DACCLK
input.
1
4
REFCLK cross-correction
1 = enable differential crossing correction on the
REFCLK input.
1
PLL
Control
0x0A
7
PLL enable
1 = enable the PLL clock multiplier. The REFCLK input is
used as the PLL reference clock signal.
0
6
PLL manual enable
1 = enable manual selection of the VCO band. The correct
VCO band must be determined by the user and written to
Bits[5:0].
1
[5:0]
Manual VCO Band[5:0]
Selects the VCO band to be used.
000000
0x0C
[7:6]
PLL Loop Bandwidth[1:0]
Selects the PLL loop filter bandwidth.
11
00 = widest bandwidth.
…
11 = narrowest bandwidth.
[4:0]
PLL Charge Pump
Current[4:0]
Sets the nominal PLL charge pump current.
10001
00000 = lowest current setting.
…
11111 = highest current setting.
0x0D
[7:6]
N2[1:0]
PLL control clock divider. This divider determines the ratio
of the DACCLK frequency to the PLL controller clock
frequency. fPC_CLK must always be less than 75 MHz.
11
00 = fDACCLK/fPC_CLK = 2.
01 = fDACCLK/fPC_CLK = 4.
10 = fDACCLK/fPC_CLK = 8.
11 = fDACCLK/fPC_CLK = 16.
4
PLL cross-control enable
1 = enable PLL cross-point controller.
1
[3:2]
N0[1:0]
PLL VCO divider. This divider determines the ratio of the
VCO frequency to the DACCLK frequency.
10
00 = fVCO/fDACCLK = 1.
01 = fVCO/fDACCLK = 2.
10 = fVCO/fDACCLK = 4.
11 = fVCO/fDACCLK = 4.
[1:0]
N1[1:0]
PLL loop divider. This divider determines the ratio of the
DACCLK frequency to the REFCLK frequency.
01
00 = fDACCLK/fREFCLK = 2.
01 = fDACCLK/fREFCLK = 4.
10 = fDACCLK/fREFCLK = 8.
11 = fDACCLK/fREFCLK = 16.
PLL Status
0x0E
7
PLL locked
1 = the PLL-generated clock is tracking the REFCLK input
signal.
N/A
[3:0]
VCO Control Voltage[3:0]
VCO control voltage readback. See Table 22.
N/A
0x0F
[5:0]
VCO Band Readback[5:0]
Indicates the VCO band currently selected.
N/A
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