參數(shù)資料
型號(hào)： AD8175ABPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/40頁(yè)
文件大?。?/td> 0K
描述： IC CROSSPOINT SWITCH TRPL 676BGA
標(biāo)準(zhǔn)包裝： 1
功能： 交叉點(diǎn)開(kāi)關(guān)
電路： 3 x 16:9
電壓電源： 單/雙電源
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 5.5 V，±2.5V
電流 - 電源： 600mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-BGA（27x27）
包裝： 管件
Data Sheet
AD8175
Rev. B | Page 29 of 40
If more than one AD8175 device is to be serially programmed
in a system, the SEROUT signal from one device can be
connected to the SERIN of the next device to form a serial
chain. All of the CLK, UPDATE, and SER/PAR pins should be
connected in parallel and operated as described above. The
serial data is input to the SERIN pin of the first device of the
chain, and it will ripple through to the last. Therefore, the data
for the last device in the chain should come at the beginning of
the programming sequence. The length of the programming
sequence is 45 bits times the number of devices in the chain. CS
gates the CLK and UPDATE signals, so that when CS is held
high, both CLK and UPDATE are held in their inactive high
state, while when CS is held low, both CLK and UPDATE
function normally.
Parallel Programming Description
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the
matrix. In fact, parallel programming allows the modification of
a single output or more at a time. Since this takes only one
WE/UPDATE cycle, significant time savings can be realized by
using parallel programming.
One important consideration in using parallel programming is
that the RST signal does not reset all registers in the AD8175.
When taken low, the RST signal only sets each output to the
disabled state. This is helpful during power-up to ensure that
two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device
generally have random data, even though the RST signal has
been asserted. If parallel programming is used to program one
output, then that output will be properly programmed, but the
rest of the device will have a random program state depending
on the internal register content at power-up. Therefore, when
using parallel programming, it is essential that all outputs be
programmed to a desired state after power-up. This ensures that
the programming matrix is always in a known state. From then
on, parallel programming can be used to modify a single output
or more at a time.
In similar fashion, if UPDATE is taken low after initial power-
up, the random power-up data in the shift register will be
programmed into the matrix. Therefore, in order to prevent the
crosspoint from being programmed into an unknown state, do
not apply a logic level to UPDATE after power is initially
applied. Programming the full shift register once to a desired
state, by either serial or parallel programming after initial
power-up, eliminates the possibility of programming the matrix
to an unknown state.
The Chip select (CS) feature is not applicable in parallel
programming mode; in other words, it is possible to program
the AD8175 in parallel mode when the part is deselected. Refer
to the logic diagram shown in Figure 7, which shows that the
CS feature gates the serial clock and has no bearing on parallel
mode programming. Shared WE lines should therefore not be
used in parallel programming mode. To change an output’s
programming via parallel programming, SER/PAR, UPDATE,
and CLK should all be taken high. The parallel clock, WE,
should start in the high state. The 4-bit address of the output to
be programmed should be put on A3 to A0. Data Bit D3 to Data
Bit D0 should contain the information that identifies the input
that gets programmed to the output that is addressed. Data Bit
D4 determines the enabled state of the output. If D4 is low
(output disabled), then the data on D3 to D0 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a high-to-low
transition of the WE signal. The matrix is not programmed,
however, until the UPDATE signal is taken low. It is thus
possible to latch in new data for several or all of the outputs first
via successive negative transitions of WE while UPDATE is held
high, and then have all the new data take effect when UPDATE
goes low. This is the technique that should be used when
programming the device for the first time after power-up when
using parallel programming.
Reset
When powering up the AD8175, it is usually desirable to have
the outputs come up in the disabled state. The RST pin, when
taken low, causes all outputs to be in the disabled state.
However, the RST signal does not reset all registers in the
AD8175. This is important when operating in the parallel
programming mode. Refer to the Serial Programming
Description section for information about programming
internal registers after power-up. Serial programming programs
the entire matrix each time, so no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply a logic low
signal to UPDATE initially after power-up. The shift register
should first be loaded with the desired data, and only then can
the UPDATE be taken low to program the device.
The RST pin has a 20 kΩ pull-up resistor to VDD that can be
used to create a simple power-up reset circuit. A capacitor from
RST to ground holds RST low for some time while the rest of
the device stabilizes. The low condition causes all the outputs to
be disabled. The capacitor then charges through the pull-up
resistor to the high state, thus allowing full programming
capability of the device.
Broadcast
The AD8175 logic interface has a broadcast mode, in which all
first rank latches can be simultaneously parallel-programmed to
the same data in one write-cycle. This is especially useful in
clearing random first rank data after power-up. To access the
broadcast mode, the part is parallel-programmed using the
device pins WE, A0 to A3, D0 to D4 and UPDATE. The only
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