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參數(shù)資料
| 型號： | AD8117 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Video Crosspoint Switch Video Crosspoint Switch |
| 中文描述： | 視頻交叉點開關(guān)視頻交叉點開關(guān) |
| 文件頁數(shù)： | 20/32頁 |
| 文件大小： | 488K |
| 代理商： | AD8117 |
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AD8117/AD8118
Preliminary Technical Data
After the desired address and data signals have been
established, they can be latched into the shift register by a high
to low transition of the WE signal. The matrix will not be
programmed, however, until the UPDATE signal is taken low.
It is thus possible to latch in new data for several or all of the
outputs first via successive negative transitions of WE while
UPDATE is held HIGH, and then have all the new data take
effect when UPDATE goes LOW. This is the technique that
should be used when programming the device for the first time
after power-up when using parallel programming.
Rev. PrA | Page 20 of 32
Reset
When powering up the AD8117, it is usually desirable to have
the outputs come up in the disabled state. The RESET
pin,
when taken LOW, will cause all outputs to be in the disabled
state. However, the RESET
signal does not reset all registers in
the AD8117. This is important when operating in the parallel
programming mode. Please refer to that section for
information about programming internal registers after power-
up. Serial programming will program the entire matrix each
time, so no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply a logic low
signal to UPDATE
initially after power-up. The shift register
should first be loaded with the desired data, and then UPDATE
can be taken LOW to program the device.
The RESET pin has a 20 kΩ pull-up resistor to VDD that can be
used to create a simple power-up reset circuit. A capacitor from
RESET to ground will hold RESET
low for some time while the
rest of the device stabilizes. The low condition will cause all the
outputs to be disabled. The capacitor will then charge through
the pull-up resistor to the high state, thus allowing full
programming capability of the device.
Broadcast
The AD8117 logic interface has a broadcast mode, in which all
first rank latches can be simultaneously parallel-programmed to
the same data in one write-cycle. This is especially useful in
clearing random first rank data after power-up. To access the
broadcast mode, the part is parallel-programmed using the
device pins WE, A0–A4, D0–A5 and UPDATE. The only
difference is that the SER/PAR pin is held LOW, as if serial
programming. By holding CLK high, no serial clocking will
occur, and instead the WE can be used to clock all first rank
latches in the chip at once.
OPERATING MODES
The AD8117/AD8118 has fully-differential inputs and outputs.
The inputs and outputs can also be operated in a single-ended
fashion. This presents several options for circuit configurations
that will require different gains and treatment of terminations, if
they are used.
Differential Input
The AD8117/AD8118 has differential input receivers. These
receivers allow the user to drive the inputs with a differential
signal with an uncertain common-mode voltage, such as from a
remote source over twisted pair. The receivers will respond
only to the difference in input voltages, and will restore a
common-mode voltage suitable for the internal signal path.
Noise or crosstalk that is present in both inputs will be rejected
by the input stage, as specified by its common-mode rejection
ratio (CMRR). Differential operation offers a great noise
benefit for signals that are propagated over distance in a noisy
environment.
RCVR
RG
OUT-
OUT+
IN+
VOCM
IN-
RG
RF
RF
to switch matrix
Figure 22. Input Receiver Equivalent Circuit
The circuit configuration used by the differential input receivers
is similar to that of several Analog Devices general-purpose
differential amplifiers, such as the AD8131. It is a voltage-
feedback amplifier with internal gain setting resistors. The
arrangement of feedback makes the differential input
impedance appear to be 5 kΩ across the inputs.
This impedance will create a small differential termination
error if the user does not account for the 5 kΩ parallel element,
although this error will be less than 1% in most cases.
Additionally, the source impedance driving the AD8117
appears in parallel with the internal gain-setting resistors, such
that there may be a gain error for some values of source
resistance. The AD8117/AD8118 are adjusted such that their
gains will be correct when driven by a back-terminated 75 Ω
source impedance at each input phase (37.5 Ω effective
impedance to ground at each input pin, or 75 Ω differential
source impedance across pairs of input pins). If a different
source impedance is presented, the differential gain of the
AD8117/AD8118 can be calculated by
R
IN, dm
= 2 ×
R
G
= 5 kΩ
G
dm
=
R
F
R
G
+
R
S
V
OUT, dm
V
IN, dm
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8117_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:600 MHz, 32 】 32 Buffered Analog Crosspoint Switch |
| AD8117ABPZ | 功能描述:IC CROSSPOINT SWIT 32X32 304BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8117-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:600 MHz, 32 】 32 Buffered Analog Crosspoint Switch |
| AD8118 | 制造商:AD 制造商全稱:Analog Devices 功能描述:600 MHz, 32 】 32 Buffered Analog Crosspoint Switch |
| AD8118ABPZ | 功能描述:IC CROSSPOINT SWIT 32X32 304BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
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