參數(shù)資料
型號(hào)： AD8117
廠商： Analog Devices, Inc.
英文描述： Video Crosspoint Switch Video Crosspoint Switch
中文描述： 視頻交叉點(diǎn)開(kāi)關(guān)視頻交叉點(diǎn)開(kāi)關(guān)
文件頁(yè)數(shù)： 18/32頁(yè)
文件大小： 488K
代理商： AD8117
AD8117/AD8118
Preliminary Technical Data
THEORY OF OPERATION
Rev. PrA | Page 18 of 32
The AD8117 is a fully-differential crosspoint array with 32
outputs, each of which can be connected to any one of 32
inputs. Organized by output row, 32 switchable input
transconductance stages are connected to each output buffer to
form 32-to-1 multiplexers. There are 32 of these multiplexers,
each with its inputs wired in parallel, for a total array of 1,024
transconductance stages forming a multicast-capable crosspoint
switch.
Decoding logic for each output selects one (or none) of the
transconductance stages to drive the output stage. The enabled
transconductance stage drives the output stage, and feedback
forms a closed-loop amplifier with a differential gain of one (the
difference between the output voltages is equal to the difference
between the input voltages). A second feedback loop controls
the common-mode output level, forcing the average of the
differential output voltages to match the voltage on the VOCM
reference pin. Although each output has an independent
common-mode control loop, the VOCM reference is common
for the entire chip, and as such needs to be driven with a low
impedance to avoid crosstalk.
Each differential input to the AD8117 is buffered by a receiver.
The purpose of this receiver is to provide an extended input
common-mode range, and to remove this common-mode from
the signal chain. Like the output multiplexers, the input
receiver has both a differential loop and a common-mode
control loop. A mask-programmable feedback network sets the
closed-loop differential gain. For the AD8117, this differential
gain is one, and for the AD8118, this is a differential gain of
two. The receiver has an input stage that does not respond to
the common-mode of the signal. This architecture, along with
the attenuating feedback network, allows the user to apply input
voltages that extend from rail-to-rail. Excess differential loop
gain-bandwidth product reduces the effect of the closed-loop
gain on the bandwidth of the device.
The output stage of the AD8117 is designed for low differential
gain and phase error when driving composite video signals. It
also provides slew current for fast pulse response when driving
component video signals. Unlike many multiplexer designs,
these requirements are balanced such that large signal
bandwidth is very similar to small signal bandwidth. The
design load is 150 Ω, but provisions are made to drive loads as
low as 75 Ω so long as on-chip power dissipation limits are not
exceeded.
The outputs of the AD8117 can be disabled to minimize on-
chip power dissipation. When disabled, there is only a
common-mode feedback network of 30kΩ between the
differential outputs. This high impedance allows multiple ICs
to be bussed together without additional buffering. Care must
be taken to reduce output capacitance, which will result in more
overshoot and frequency-domain peaking. A series of internal
amplifiers drive internal nodes such that a wide-band high-
impedance is presented at the disabled output, even while the
output bus is under large signal swings. When the outputs are
disabled and driven externally, the voltage applied to them
should not exceed the valid output swing range for the AD8117
in order to keep these internal amplifiers in their linear range of
operation. Applying excess differential voltages to the disabled
outputs can cause damage to the AD8117 and should be
avoided (see the Absolute Maximum Ratings section of this
datasheet for guidelines).
The connection of the AD8117 is controlled by a flexible TTL
compatible logic interface. Either parallel or serial loading into
a first rank of latches preprograms each output. A global
update signal moves the programming data into the second
rank of latches, simultaneously updating all outputs. In serial
mode, a serial-out pin allows devices to be daisy chained
together for single-pin programming of multiple ICs. A power-
on reset pin is available to avoid bus conflicts by disabling all
outputs. This power-on reset clears the second rank of latches,
but does not clear the first rank of latches. In parallel mode, to
quickly clear the first rank, a broadcast parallel programming
feature is available. In serial-mode, pre-programming
individual inputs is not possible and the entire shift register
needs to be flushed.
The AD8117 can operate on a single +5 V supply, powering
both the signal path (with the VPOS/VNEG supply pins), and
the control logic interface (with the VDD/DGND supply pins).
But in order to easily interface to ground-referenced video
signals, split supply operation is possible with
±
2.5 V supplies.
In this case, a flexible logic interface allows the control logic
supplies (VDD/DGND) to be run off +2 V/0 V to +3.3 V/0 V
while the core remains on split supplies. Additional flexibility
in the analog output common-mode level facilitates unequal
split supplies. If +3 V/–2 V supplies to +2 V/–3 V supplies are
desired, the VOCM pin can still be set to 0 V for ground-
referenced video signals.
相關(guān)PDF資料
PDF描述
AD811 High Performance Video Op Amp(高性能視頻運(yùn)放)
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AD8123ACPZ-R7 Triple Differential Receiver with Adjustable Line Equalization
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD8117_07 制造商:AD 制造商全稱:Analog Devices 功能描述:600 MHz, 32 】 32 Buffered Analog Crosspoint Switch
AD8117ABPZ 功能描述:IC CROSSPOINT SWIT 32X32 304BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開(kāi)關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR)
AD8117-EVAL 制造商:AD 制造商全稱:Analog Devices 功能描述:600 MHz, 32 】 32 Buffered Analog Crosspoint Switch
AD8118 制造商:AD 制造商全稱:Analog Devices 功能描述:600 MHz, 32 】 32 Buffered Analog Crosspoint Switch
AD8118ABPZ 功能描述:IC CROSSPOINT SWIT 32X32 304BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開(kāi)關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR)
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