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參數(shù)資料
| 型號： | AD7453BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT W/DIFF INP SOT23-8 |
| 設(shè)計資源： | Measuring -48 V High-Side Current Using AD629, AD8603, AD780, and AD7453 (CN0100) |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 555k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，雙極 |
AD7453
Rev. B | Page 15 of 20
MODES OF OPERATION
The mode of operation of the AD7453 is selected by controlling
the logic state of the CS signal during a conversion. There are
two possible modes of operation, normal mode and power-
down mode. The point at which CS is pulled high after the
conversion has been initiated determines whether the AD7453
enters power-down mode. Similarly, if already in power-down,
CS controls whether the device returns to normal operation or
remains in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/ throughput
rate ratio for differing application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7453 remaining fully powered up all the time. Figure 24
shows the general diagram of the operation of the AD7453 in
this mode. The conversion is initiated on the falling edge of CS,
as described in the Serial Interface section. To ensure that the
part remains fully powered up, CS must remain low until at
least 10 SCLK falling edges have elapsed after the falling edge
of CS.
If CS is brought high any time after the 10th SCLK falling edge
but before the 16th SCLK falling edge, the part remains powered
up but the conversion is terminated and SDATA goes back into
three-state. Sixteen serial clock cycles are required to complete
the conversion and access the complete conversion result. CS
may idle high until the next conversion, or may idle low until
some time prior to the next conversion. Once a data transfer is
complete, i.e., when SDATA has returned to three-state, another
conversion can be initiated after the quiet time, tQUIET, has
elapsed by again bringing CS low.
110
CS
SCLK
SDATA
16
4 LEADING ZEROS + CONVERSION RESULT
03155-A
-024
Figure 24. Normal Mode Operation
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required—the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7453 is in power-
down mode, all analog circuitry is powered down. For the
AD7453 to enter power-down mode, the conversion process
must be interrupted by bringing CS high anywhere after the
second falling edge of SCLK and before the 10th falling edge of
SCLK, as shown in Figure 25.
Once CS has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of CS is terminated, and SDATA goes back into
three-state. The time from the rising edge of CS to SDATA
Specifications). If CS is brought high before the second SCLK
falling edge, the part remains in normal mode and does not
power down. This avoids accidental power-down due to glitches
on the CS line.
To exit this mode of operation and power up the AD7453 again,
a dummy conversion is performed. On the falling edge of CS,
the device begins to power up, and continues to power up as
long as CS is held low until after the falling edge of the 10th
SCLK. The device is fully powered up after 1 s has elapsed and,
as shown in Figure 26, valid data results from the next
conversion.
If CS is brought high before the 10th falling edge of SCLK, the
AD7453 again goes back into power-down. This avoids
accidental power-up due to glitches on the CS line or an
inadvertent burst of eight SCLK cycles while CS is low. So
although the device may begin to power up on the falling edge
of CS, it again powers down on the rising edge of CS as long as
it occurs before the 10th SCLK falling edge.
1
10
CS
SCLK
SDATA
THREE-STATE
2
03155-A
-025
Figure 25. Entering Power-Down Mode
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