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參數(shù)資料
| 型號： | AD7453BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT W/DIFF INP SOT23-8 |
| 設(shè)計資源： | Measuring -48 V High-Side Current Using AD629, AD8603, AD780, and AD7453 (CN0100) |
| 標準包裝： | 3,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 555k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，雙極 |
AD7453
Rev. B | Page 13 of 20
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades.
Figure 20 shows a graph of the THD versus analog input signal
frequency for different source impedances.
INPUT FREQUENCY (kHz)
–100
10
THD
(dB)
100
277
–80
–50
–40
0
200
–10
–20
–30
–60
–70
–90
10
62
100
03155-A
-020
Figure 20. THD vs. Analog Input Frequency for Various Source Impedances
Figure 21 shows a graph of THD versus analog input frequency
for various supply voltages while sampling at 555 kSPS with an
SCLK of 10 MHz. In this case, the source impedance is 10 .
–90
10
THD
(dBs
)
TA = 25°C
VDD = 2.7V
VDD = 3.6V
VDD = 4.75V
VDD = 5.25V
100
277
–85
–80
–75
–70
–65
–60
–55
–50
INPUT FREQUENCY (kHz)
03155-A
-021
Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
DIGITAL INPUTS
The digital inputs applied to the AD7453 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied, i.e., CS and SCLK, can go to 7 V and are
not restricted by the VDD + 0.3 V limits as on the analog input.
The main advantage of the inputs not being restricted to the
VDD + 0.3 V limit is that power supply sequencing issues are
avoided. If CS or SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs if a signal
greater than 0.3 V were applied prior to VDD.
REFERENCE
An external source is required to supply the reference to the
AD7453. This reference input can range from 100 mV to VDD.
The specified reference is 2.5 V for the 2.7 V to 5.25 V power
supply range. The reference input chosen for an application
should never be greater than the power supply. Errors in the
reference source result in gain errors in the AD7453 transfer
function. A capacitor of at least 0.1 F should be placed on the
VREF pin. Suitable reference sources for the AD7453 include the
AD780 and the ADR421. Figure 22 shows a typical connection
diagram for the VREF pin.
1
AD780
NC
8
2
VIN
NC
7
3
GND
6
4
TEMP
5
OPSEL
TRIM
VOUT
AD7453*
VREF
2.5V
NC
VDD
NC
VDD
NC = NO CONNECT
10nF
0.1
F
0.1
F
0.1
F
03155-A
-022
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Typical VREF Connection Diagram for VDD = 5 V
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram of the serial interface
of the AD7453. The serial clock provides the conversion clock
and controls the transfer of data from the device during
conversion. CS initiates the conversion process and frames the
data transfer. The falling edge of CS puts the track-and-hold
into hold mode and takes the bus out of three-state. The analog
input is sampled and the conversion is initiated at this point.
The conversion requires 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
shown at Point B in Figure 2. On the 16th SCLK falling edge, the
SDATA line goes back into three-state.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion is terminated and the SDATA line goes back into
three-state.
The conversion result from the AD7453 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7453 consists of four leading zeros, followed by 12 bits of
conversion data, provided MSB first. The output coding is
straight (natural) binary.
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