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參數(shù)資料
| 型號： | AD7453BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT W/DIFF INP SOT23-8 |
| 設(shè)計資源： | Measuring -48 V High-Side Current Using AD629, AD8603, AD780, and AD7453 (CN0100) |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 555k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，雙極 |
AD7453
Rev. B | Page 17 of 20
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7453 when not con-
verting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 27 shows how, as the through-
put rate is reduced, the device remains in its power-down state
longer and the average power consumption reduces accordingly.
For example, if the AD7453 is operated in continuous sampling
mode with a throughput rate of 100 kSPS and a 10 MHz SCLK,
and the device is placed in the power-down mode between con-
versions, then the power consumption is calculated as follows:
Power dissipation during normal operation = 7.25 mW max (for
VDD = 5 V).
If the power-up time is one dummy cycle (1.06 s if CS is
brought high after the 10th SCLK falling edge in the cycle and
then brought low after the quiet time) and the remaining
conversion time is another cycle (1.6 s), then the AD7453 can
be said to dissipate 7.25 mW for 2.66 s
during each
conversion cycle.
If the throughput rate = 100 kSPS, then the cycle time = 10 s
and the average power dissipated during each cycle is
(2.66/10) × 7.25 mW = 1.92 mW
For the same scenario, if VDD = 3 V, the power dissipation during
normal operation is 3.3 mW max. The AD7453 can now be said
to dissipate 3.3 mW for 2.66 s
during each conversion cycle.
The average power dissipated during each cycle with a
throughput rate of 100 kSPS is therefore
(2.66/10) × 3.3 mW = 0.88 mW
This is how the power numbers in Figure 27 are calculated.
THROUGHPUT (kSPS)
100
0
350
P
O
WE
R
(mW)
0.01
50
100
150
200
250
300
0.1
1
10
VDD = 5V
VDD = 3V
03155-A
-027
Figure 27. Power vs. Throughput Rate for Power-Down Mode
This figure assumes a very short time to enter power-down mode. This
increases as the burst of clocks used to enter power down mode is
increased.
For throughput rates above 320 kSPS, the serial clock frequency
should be reduced for optimum power performance.
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7453 allows the part to be con-
nected directly to a range of different microprocessors. This
section explains how to interface the AD7453 with some of the
more common microcontroller and DSP serial interface
protocols.
AD7453 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7453 without any glue logic required.
The SPORT control register should be set up as follows:
TFSW = RFSW = 1
Alternate Framing
INVRFS = INVTFS = 1
Active Low Frame Signal
DTYPE = 00
Right Justify Data
SLEN = 1111
16-Bit Data-Words
ISCLK = 1
Internal Serial Clock
TFSR = RFSR = 1
Frame Every Word
IRFS = 0
ITFS = 1
To implement power-down mode, SLEN should be set to 1001
to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 28. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS, and, as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this
example, the timer interrupt is used to control the sampling rate
of the ADC, and, under certain conditions, equidistant sampling
may not be achieved.
AD7453*
ADSP-21xx*
SCLK
DR
RFS
TFS
SCLK
SDATA
CS
03155-A
-028
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 28. Interfacing to the ADSP-21xx
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