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參數(shù)資料
| 型號： | AD7453BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/DIFF INP SOT23-8 |
| 設(shè)計資源： | Measuring -48 V High-Side Current Using AD629, AD8603, AD780, and AD7453 (CN0100) |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 555k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，雙極 |
AD7453
Rev. B | Page 14 of 20
Timing Example 1
Sixteen serial clock cycles are required to perform a conversion
and to access data from the AD7453. CS going low provides the
first leading zero to be read in by the microcontroller or DSP.
The remaining data is then clocked out on the subsequent
SCLK falling edges, beginning with the second leading zero.
Thus the first falling clock edge on the serial clock provides the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having been clocked out on the previous
(15th) falling edge. Once the conversion is complete and the data
has been accessed after the 16 clock cycles, it is important to
ensure that, before the next conversion is initiated, enough time
is left to meet the acquisition and quiet time specifications. See
Having FSCLK = 10 MHz and a throughput rate of 555 kSPS gives
a cycle time of
1/Throughput = 1/555,000 = 1.8 s
A cycle consists of
t2 + 12.5(1/FSCLK) + tACQ = 1.8 s
Therefore if t2 = 10 ns,
10 ns + 12.5(1/10 MHz) + tACQ = 1.8 s
tACQ = 540 ns
This 540 ns satisfies the requirement of 290 ns for tACQ. From
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, i.e., the first rising edge of SCLK
after the CS falling edge would have the leading zero provided,
and the 15th SCLK edge would have DB0 provided.
2.5(1/FSCLK) + t8 + tQUIET
where t8 = 35 ns. This allows a value of 255 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
t2
t8
t6
t5
tCONVERT
CS
SCLK
12
3
4
5
13
14
15
16
03155-A
-023
12.5(1/FSCLK)
tACQUISITION
1/THROUGHPUT
tQUIET
10ns
Figure 23. Serial Interface Timing Example
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7457 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Pseudo Differential, 100 kSPS 12-Bit ADC in an 8-Lead SOT-23 |
| AD7457_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Pseudo Differential, 100 kSPS |
| AD7457BRT | 制造商:Analog Devices 功能描述: |
| AD7457BRT-R2 | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Serial 8-Pin SOT-23 T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT P/DIFF I/PUT, 100KSPS ADC I.C. - Bulk |
| AD7457BRT-REEL | 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 12-BIT SERL 8PIN SOT-23 - Tape and Reel |
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