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參數(shù)資料
| 型號： | AD73322LARUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONTEND DL 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 4 |
| 功率（瓦特）： | 73mW |
| 電壓 - 電源，模擬： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD73322
–37–
REV. B
APPENDIX A
DAC Timing Control Example
The AD73322’s DAC is loaded from the DAC register contents
just before the ADC register contents are loaded to the serial
register (SDOFS going high). This default DAC load position
can be advanced in time to occur earlier with respect to the
SDOFS going high. Figure 45 shows an example of the ADC
unload and DAC load sequence. At time t1 the SDOFS is raised
to indicate that a new ADC word is ready. Following the SDOFS
pulse, 16 bits of ADC data are clocked out on SDO in the sub-
sequent 16 SCLK cycles finishing at time t2 where the DSP’s
SPORT will have received the 16-bit word. The DSP may
process this information and generate a DAC word to be sent to
SE
SCLK
SDOFS
SDO
SDIFS
DATA REGISTER
UPDATE
DAC LOAD
FROM DAC REGISTER
t1
t2
t3
t4 t6
t5
ADC WORD
SDI
DAC WORD
Figure 43. DAC Timing Control
the AD73322. Time t3 marks the beginning of the sequence of
sending the DAC word to the AD73322. This sequence ends at
time t4 where the DAC register will be updated from the 16 bits
in the AD73322’s serial register. However, the DAC will not be
updated from the DAC register until time t5, which may not be
acceptable in certain applications. In order to reduce this delay
and load the DAC at time t6, the DAC advance register can be
programmed with a suitable setting corresponding to the
required time advance (refer to Table XI for details of DAC
Timing Control settings).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD73322LARZ | 功能描述:IC ANALOG FRONT END DUAL 28-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73322LARZ-REEL | 制造商:Analog Devices 功能描述:DUAL-CHANNEL, 3 V FRONT-END PROCESSOR FOR GENERAL PURPOSE - Tape and Reel |
| AD73322LAST | 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel 制造商:Analog Devices 功能描述: |
| AD73322LAST-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 44-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel |
| AD73322LASTZ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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